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Merge pull request #156 from JonasDann/feature/interface-assertions
Feature/interface assertions
2 parents fd2e64c + 08faa27 commit b3728f6

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‎examples/01_hello_world/hw/src/hdl/perf_local.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,10 +48,10 @@ module perf_local (
4848
);
4949

5050
// Simple pipeline stages, buffering the input/output signals (not really needed, but nice to have for easier timing closure)
51-
AXI4SR axis_in_int();
51+
AXI4SR axis_in_int (.*);
5252
axisr_reg inst_reg_sink (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_in), .m_axis(axis_in_int));
5353

54-
AXI4SR axis_out_int();
54+
AXI4SR axis_out_int (.*);
5555
axisr_reg inst_reg_src (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_out_int), .m_axis(axis_out));
5656

5757
// User logic; adding 1 to the input stream and writing it to the output stream

‎examples/07_perf_fpga/hw/src/vfpga_top.svh‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,10 +25,10 @@
2525
*/
2626

2727
// Simple pipeline stages, buffering the input/output signals (not really needed, but nice to have for easier timing closure)
28-
AXI4SR axis_in_int();
28+
AXI4SR axis_in_int (.*);
2929
axisr_reg inst_reg_in (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_host_recv[0]), .m_axis(axis_in_int));
3030

31-
AXI4SR axis_out_int();
31+
AXI4SR axis_out_int (.*);
3232
axisr_reg inst_reg_out (.aclk(aclk), .aresetn(aresetn), .s_axis(axis_out_int), .m_axis(axis_host_send[0]));
3333

3434
///////////////////////////////////////

‎hw/hdl/common/arbiters/dma_arbiter.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,8 @@ logic done_src;
6767
logic [N_SPLIT_CHAN_BITS-1:0] rr_reg;
6868
logic [N_SPLIT_CHAN_BITS-1:0] vfid;
6969

70-
metaIntf #(.STYPE(logic[1+N_SPLIT_CHAN_BITS+BLEN_BITS-1:0])) user_seq_in ();
71-
metaIntf #(.STYPE(logic[N_SPLIT_CHAN_BITS-1:0])) done_seq_in ();
70+
metaIntf #(.STYPE(logic[1+N_SPLIT_CHAN_BITS+BLEN_BITS-1:0])) user_seq_in (.*);
71+
metaIntf #(.STYPE(logic[N_SPLIT_CHAN_BITS-1:0])) done_seq_in (.*);
7272
logic [N_SPLIT_CHAN_BITS-1:0] done_vfid;
7373

7474
logic [BLEN_BITS-1:0] n_tr;

‎hw/hdl/common/regs/axil_reg_array.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ module axil_reg_array #(
4444
// -----------------------------------------------------------------------------------------------------------------------
4545
// Register slices
4646
// -----------------------------------------------------------------------------------------------------------------------
47-
AXI4L axi_s [N_STAGES+1] ();
47+
AXI4L axi_s [N_STAGES+1] (.*);
4848

4949
`AXIL_ASSIGN(s_axi, axi_s[0])
5050
`AXIL_ASSIGN(axi_s[N_STAGES], m_axi)

‎hw/hdl/common/regs/axis_reg_array.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ module axis_reg_array #(
4444
// -----------------------------------------------------------------------------------------------------------------------
4545
// -- Register slices ----------------------------------------------------------------------------------------------------
4646
// -----------------------------------------------------------------------------------------------------------------------
47-
AXI4S axis_s [N_STAGES+1] ();
47+
AXI4S axis_s [N_STAGES+1] (.*);
4848

4949
`AXIS_ASSIGN(s_axis, axis_s[0])
5050
`AXIS_ASSIGN(axis_s[N_STAGES], m_axis)

‎hw/hdl/common/regs/meta_reg_array.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ module meta_reg_array #(
4242
// -----------------------------------------------------------------------------------------------------------------------
4343
// -- Register slices ----------------------------------------------------------------------------------------------------
4444
// -----------------------------------------------------------------------------------------------------------------------
45-
metaIntf #(.STYPE(logic[DATA_BITS-1:0])) meta_s [N_STAGES+1] ();
45+
metaIntf #(.STYPE(logic[DATA_BITS-1:0])) meta_s [N_STAGES+1] (.*);
4646

4747
`META_ASSIGN(s_meta, meta_s[0])
4848
`META_ASSIGN(meta_s[N_STAGES], m_meta)

‎hw/hdl/mmu/mmu_arbiter.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,8 @@ logic done_src;
6868
logic [N_REGIONS_BITS-1:0] rr_reg;
6969
logic [N_REGIONS_BITS-1:0] vfid;
7070

71-
metaIntf #(.STYPE(logic[1+N_REGIONS_BITS+BLEN_BITS-1:0])) user_seq_in ();
72-
metaIntf #(.STYPE(logic[N_REGIONS_BITS-1:0])) done_seq_in ();
71+
metaIntf #(.STYPE(logic[1+N_REGIONS_BITS+BLEN_BITS-1:0])) user_seq_in (.*);
72+
metaIntf #(.STYPE(logic[N_REGIONS_BITS-1:0])) done_seq_in (.*);
7373
logic [N_REGIONS_BITS-1:0] done_vfid;
7474

7575
logic [BLEN_BITS-1:0] n_tr;

‎hw/hdl/mmu/mmu_arbiter_isr.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ logic done_src;
6363
logic [N_REGIONS_BITS-1:0] rr_reg;
6464
logic [N_REGIONS_BITS-1:0] vfid;
6565

66-
metaIntf #(.STYPE(logic[N_REGIONS_BITS-1:0])) done_seq_in ();
66+
metaIntf #(.STYPE(logic[N_REGIONS_BITS-1:0])) done_seq_in (.*);
6767
logic [N_REGIONS_BITS-1:0] done_vfid;
6868

6969
// --------------------------------------------------------------------------------

‎hw/hdl/mmu/mmu_credits_rd.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -69,8 +69,8 @@ logic req_done;
6969

7070
logic [BLEN_BITS-1:0] rd_len;
7171

72-
metaIntf #(.STYPE(logic[BLEN_BITS-1:0])) req_que_in ();
73-
metaIntf #(.STYPE(logic[BLEN_BITS-1:0])) req_que_out ();
72+
metaIntf #(.STYPE(logic[BLEN_BITS-1:0])) req_que_in (.*);
73+
metaIntf #(.STYPE(logic[BLEN_BITS-1:0])) req_que_out (.*);
7474

7575
// -- REG
7676
always_ff @(posedge aclk) begin: PROC_REG

‎hw/hdl/mmu/mmu_region_top.sv‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -112,12 +112,12 @@ tlbIntf #(.TLB_INTF_DATA_BITS(TLB_S_DATA_BITS)) wr_sTlb ();
112112
tlbIntf #(.TLB_INTF_DATA_BITS(TLB_L_DATA_BITS)) lTlb ();
113113
tlbIntf #(.TLB_INTF_DATA_BITS(TLB_S_DATA_BITS)) sTlb ();
114114

115-
AXI4S #(.AXI4S_DATA_BITS(AXI_TLB_BITS)) axis_lTlb ();
116-
AXI4S #(.AXI4S_DATA_BITS(AXI_TLB_BITS)) axis_sTlb ();
115+
AXI4S #(.AXI4S_DATA_BITS(AXI_TLB_BITS)) axis_lTlb (.*);
116+
AXI4S #(.AXI4S_DATA_BITS(AXI_TLB_BITS)) axis_sTlb (.*);
117117

118118
// Request interfaces
119-
metaIntf #(.STYPE(req_t)) rd_req ();
120-
metaIntf #(.STYPE(req_t)) wr_req ();
119+
metaIntf #(.STYPE(req_t)) rd_req (.*);
120+
metaIntf #(.STYPE(req_t)) wr_req (.*);
121121

122122
// ----------------------------------------------------------------------------------------
123123
// Mutex

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