@@ -28,9 +28,36 @@ properties:
2828 - description : PCIe 5 pipe clock
2929 - description : PCIe 6a pipe clock
3030 - description : PCIe 6b pipe clock
31- - description : USB QMP Phy 0 clock source
32- - description : USB QMP Phy 1 clock source
33- - description : USB QMP Phy 2 clock source
31+ - description : USB4_0 QMPPHY clock source
32+ - description : USB4_1 QMPPHY clock source
33+ - description : USB4_2 QMPPHY clock source
34+ - description : USB4_0 PHY DP0 GMUX clock source
35+ - description : USB4_0 PHY DP1 GMUX clock source
36+ - description : USB4_0 PHY PCIE PIPEGMUX clock source
37+ - description : USB4_0 PHY PIPEGMUX clock source
38+ - description : USB4_0 PHY SYS PCIE PIPEGMUX clock source
39+ - description : USB4_1 PHY DP0 GMUX 2 clock source
40+ - description : USB4_1 PHY DP1 GMUX 2 clock source
41+ - description : USB4_1 PHY PCIE PIPEGMUX clock source
42+ - description : USB4_1 PHY PIPEGMUX clock source
43+ - description : USB4_1 PHY SYS PCIE PIPEGMUX clock source
44+ - description : USB4_2 PHY DP0 GMUX 2 clock source
45+ - description : USB4_2 PHY DP1 GMUX 2 clock source
46+ - description : USB4_2 PHY PCIE PIPEGMUX clock source
47+ - description : USB4_2 PHY PIPEGMUX clock source
48+ - description : USB4_2 PHY SYS PCIE PIPEGMUX clock source
49+ - description : USB4_0 PHY RX 0 clock source
50+ - description : USB4_0 PHY RX 1 clock source
51+ - description : USB4_1 PHY RX 0 clock source
52+ - description : USB4_1 PHY RX 1 clock source
53+ - description : USB4_2 PHY RX 0 clock source
54+ - description : USB4_2 PHY RX 1 clock source
55+ - description : USB4_0 PHY PCIE PIPE clock source
56+ - description : USB4_0 PHY max PIPE clock source
57+ - description : USB4_1 PHY PCIE PIPE clock source
58+ - description : USB4_1 PHY max PIPE clock source
59+ - description : USB4_2 PHY PCIE PIPE clock source
60+ - description : USB4_2 PHY max PIPE clock source
3461
3562 power-domains :
3663 description :
@@ -63,7 +90,34 @@ examples:
6390 <&pcie6b_phy>,
6491 <&usb_1_ss0_qmpphy 0>,
6592 <&usb_1_ss1_qmpphy 1>,
66- <&usb_1_ss2_qmpphy 2>;
93+ <&usb_1_ss2_qmpphy 2>,
94+ <&usb4_0_phy_dp0_gmux_clk>,
95+ <&usb4_0_phy_dp1_gmux_clk>,
96+ <&usb4_0_phy_pcie_pipegmux_clk>,
97+ <&usb4_0_phy_pipegmux_clk>,
98+ <&usb4_0_phy_sys_pcie_pipegmux_clk>,
99+ <&usb4_1_phy_dp0_gmux_2_clk>,
100+ <&usb4_1_phy_dp1_gmux_2_clk>,
101+ <&usb4_1_phy_pcie_pipegmux_clk>,
102+ <&usb4_1_phy_pipegmux_clk>,
103+ <&usb4_1_phy_sys_pcie_pipegmux_clk>,
104+ <&usb4_2_phy_dp0_gmux_2_clk>,
105+ <&usb4_2_phy_dp1_gmux_2_clk>,
106+ <&usb4_2_phy_pcie_pipegmux_clk>,
107+ <&usb4_2_phy_pipegmux_clk>,
108+ <&usb4_2_phy_sys_pcie_pipegmux_clk>,
109+ <&usb4_0_phy_rx_0_clk>,
110+ <&usb4_0_phy_rx_1_clk>,
111+ <&usb4_1_phy_rx_0_clk>,
112+ <&usb4_1_phy_rx_1_clk>,
113+ <&usb4_2_phy_rx_0_clk>,
114+ <&usb4_2_phy_rx_1_clk>,
115+ <&usb4_0_phy_pcie_pipe_clk>,
116+ <&usb4_0_phy_max_pipe_clk>,
117+ <&usb4_1_phy_pcie_pipe_clk>,
118+ <&usb4_1_phy_max_pipe_clk>,
119+ <&usb4_2_phy_pcie_pipe_clk>,
120+ <&usb4_2_phy_max_pipe_clk>;
67121 power-domains = <&rpmhpd RPMHPD_CX>;
68122 #clock-cells = <1>;
69123 #reset-cells = <1>;
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