PeepholeOpt: Remove check for subreg index on a def operand (llvm#123943)

arsenm · web-flow · commit 15c2d4baf172 · 2025-01-23T09:06:26.000+07:00
This is looking at operand 0 of a REG_SEQUENCE, which can never
have a subregister index.
diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp
@@ -426,8 +426,8 @@ class RegSequenceRewriter : public Rewriter {
 
     const MachineOperand &MODef = CopyLike.getOperand(0);
     Dst.Reg = MODef.getReg();
-    // If we have to compose sub-registers, bail.
-    return MODef.getSubReg() == 0;
+    assert(MODef.getSubReg() == 0 && "cannot have subregister def in SSA");
+    return true;
   }
 
   bool RewriteCurrentSource(Register NewReg, unsigned NewSubReg) override {

Original file line number	Diff line number	Diff line change
`@@ -426,8 +426,8 @@ class RegSequenceRewriter : public Rewriter {`
`426`	`426`
`427`	`427`	`const MachineOperand &MODef = CopyLike.getOperand(0);`
`428`	`428`	`Dst.Reg = MODef.getReg();`
`429`		`- // If we have to compose sub-registers, bail.`
`430`		`- return MODef.getSubReg() == 0;`
	`429`	`+ assert(MODef.getSubReg() == 0 && "cannot have subregister def in SSA");`
	`430`	`+ return true;`
`431`	`431`	`}`
`432`	`432`
`433`	`433`	`bool RewriteCurrentSource(Register NewReg, unsigned NewSubReg) override {`