@@ -97,32 +97,29 @@ def GRLenRI : RegInfoByHwMode<
9797 [LA32, LA64],
9898 [RegInfo<32,32,32>, RegInfo<64,64,64>]>;
9999
100- // The order of registers represents the preferred allocation sequence.
101- // Registers are listed in the order caller-save, callee-save, specials.
102- def GPR : RegisterClass<"LoongArch", [GRLenVT], 32, (add
103- // Argument registers (a0...a7)
104- (sequence "R%u", 4, 11),
105- // Temporary registers (t0...t8)
106- (sequence "R%u", 12, 20),
107- // Static register (s9/fp, s0...s8)
108- (sequence "R%u", 22, 31),
109- // Specials (r0, ra, tp, sp)
110- (sequence "R%u", 0, 3),
111- // Reserved (Non-allocatable)
112- R21
113- )> {
100+ class GPRRegisterClass<dag regList>
101+ : RegisterClass<"LoongArch", [GRLenVT], 32, regList> {
114102 let RegInfos = GRLenRI;
115103}
116104
105+ // The order of registers represents the preferred allocation sequence.
106+ // Registers are listed in the order caller-save, callee-save, specials.
107+ def GPR : GPRRegisterClass<(add // Argument registers (a0...a7)
108+ (sequence "R%u", 4, 11),
109+ // Temporary registers (t0...t8)
110+ (sequence "R%u", 12, 20),
111+ // Static register (s9/fp, s0...s8)
112+ (sequence "R%u", 22, 31),
113+ // Specials (r0, ra, tp, sp)
114+ (sequence "R%u", 0, 3),
115+ // Reserved (Non-allocatable)
116+ R21)>;
117+
117118// GPR for indirect tail calls. We can't use callee-saved registers, as they are
118119// restored to the saved value before the tail call, which would clobber a call
119120// address.
120- def GPRT : RegisterClass<"LoongArch", [GRLenVT], 32, (add
121- // a0...a7, t0...t8
122- (sequence "R%u", 4, 20)
123- )> {
124- let RegInfos = GRLenRI;
125- }
121+ def GPRT : GPRRegisterClass<(add // a0...a7, t0...t8
122+ (sequence "R%u", 4, 20))>;
126123
127124// Floating point registers
128125
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