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373 | 373 | #define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) |
374 | 374 | #define MDCR_EL2_TDRA_SHIFT 11 |
375 | 375 | #define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) |
376 | | -#define MDCR_E2PB_SHIFT 12 |
377 | | -#define MDCR_E2PB_MASK (0x3UL << MDCR_E2PB_SHIFT) |
378 | | -#define MDCR_TPMS_SHIFT 14 |
379 | | -#define MDCR_TPMS (0x1UL << MDCR_TPMS_SHIFT) |
380 | | -#define MDCR_EnSPM_SHIFT 15 |
381 | | -#define MDCR_EnSPM (0x1UL << MDCR_EnSPM_SHIFT) |
382 | | -#define MDCR_HPMD_SHIFT 17 |
383 | | -#define MDCR_HPMD (0x1UL << MDCR_HPMD_SHIFT) |
384 | | -#define MDCR_TTRF_SHIFT 19 |
385 | | -#define MDCR_TTRF (0x1UL << MDCR_TTRF_SHIFT) |
386 | | -#define MDCR_HCCD_SHIFT 23 |
387 | | -#define MDCR_HCCD (0x1UL << MDCR_HCCD_SHIFT) |
388 | | -#define MDCR_E2TB_SHIFT 24 |
389 | | -#define MDCR_E2TB_MASK (0x3UL << MDCR_E2TB_SHIFT) |
390 | | -#define MDCR_HLP_SHIFT 26 |
391 | | -#define MDCR_HLP (0x1UL << MDCR_HLP_SHIFT) |
392 | | -#define MDCR_TDCC_SHIFT 27 |
393 | | -#define MDCR_TDCC (0x1UL << MDCR_TDCC_SHIFT) |
394 | | -#define MDCR_MTPME_SHIFT 28 |
395 | | -#define MDCR_MTPME (0x1UL << MDCR_MTPME_SHIFT) |
396 | | -#define MDCR_HPMFZO_SHIFT 29 |
397 | | -#define MDCR_HPMFZO (0x1UL << MDCR_HPMFZO_SHIFT) |
398 | | -#define MDCR_PMSSE_SHIFT 30 |
399 | | -#define MDCR_PMSSE_MASK (0x3UL << MDCR_PMSSE_SHIFT) |
400 | | -#define MDCR_HPMFZS_SHIFT 36 |
401 | | -#define MDCR_HPMFZS (0x1UL << MDCR_HPMFZS_SHIFT) |
402 | | -#define MDCR_PMEE_SHIFT 40 |
403 | | -#define MDCR_PMEE_MASK (0x3UL << MDCR_PMEE_SHIFT) |
404 | | -#define MDCR_EBWE_SHIFT 43 |
405 | | -#define MDCR_EBWE (0x1UL << MDCR_EBWE_SHIFT) |
| 376 | +#define MDCR_EL2_E2PB_SHIFT 12 |
| 377 | +#define MDCR_EL2_E2PB_MASK (0x3UL << MDCR_EL2_E2PB_SHIFT) |
| 378 | +#define MDCR_EL2_TPMS_SHIFT 14 |
| 379 | +#define MDCR_EL2_TPMS (0x1UL << MDCR_EL2_TPMS_SHIFT) |
| 380 | +#define MDCR_EL2_EnSPM_SHIFT 15 |
| 381 | +#define MDCR_EL2_EnSPM (0x1UL << MDCR_EL2_EnSPM_SHIFT) |
| 382 | +#define MDCR_EL2_HPMD_SHIFT 17 |
| 383 | +#define MDCR_EL2_HPMD (0x1UL << MDCR_EL2_HPMD_SHIFT) |
| 384 | +#define MDCR_EL2_TTRF_SHIFT 19 |
| 385 | +#define MDCR_EL2_TTRF (0x1UL << MDCR_EL2_TTRF_SHIFT) |
| 386 | +#define MDCR_EL2_HCCD_SHIFT 23 |
| 387 | +#define MDCR_EL2_HCCD (0x1UL << MDCR_EL2_HCCD_SHIFT) |
| 388 | +#define MDCR_EL2_E2TB_SHIFT 24 |
| 389 | +#define MDCR_EL2_E2TB_MASK (0x3UL << MDCR_EL2_E2TB_SHIFT) |
| 390 | +#define MDCR_EL2_HLP_SHIFT 26 |
| 391 | +#define MDCR_EL2_HLP (0x1UL << MDCR_EL2_HLP_SHIFT) |
| 392 | +#define MDCR_EL2_TDCC_SHIFT 27 |
| 393 | +#define MDCR_EL2_TDCC (0x1UL << MDCR_EL2_TDCC_SHIFT) |
| 394 | +#define MDCR_EL2_MTPME_SHIFT 28 |
| 395 | +#define MDCR_EL2_MTPME (0x1UL << MDCR_EL2_MTPME_SHIFT) |
| 396 | +#define MDCR_EL2_HPMFZO_SHIFT 29 |
| 397 | +#define MDCR_EL2_HPMFZO (0x1UL << MDCR_EL2_HPMFZO_SHIFT) |
| 398 | +#define MDCR_EL2_PMSSE_SHIFT 30 |
| 399 | +#define MDCR_EL2_PMSSE_MASK (0x3UL << MDCR_EL2_PMSSE_SHIFT) |
| 400 | +#define MDCR_EL2_HPMFZS_SHIFT 36 |
| 401 | +#define MDCR_EL2_HPMFZS (0x1UL << MDCR_EL2_HPMFZS_SHIFT) |
| 402 | +#define MDCR_EL2_PMEE_SHIFT 40 |
| 403 | +#define MDCR_EL2_PMEE_MASK (0x3UL << MDCR_EL2_PMEE_SHIFT) |
| 404 | +#define MDCR_EL2_EBWE_SHIFT 43 |
| 405 | +#define MDCR_EL2_EBWE (0x1UL << MDCR_EL2_EBWE_SHIFT) |
406 | 406 |
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407 | 407 | #endif /* !_MACHINE_HYPERVISOR_H_ */ |
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