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AMDGPU: Allow folding multiple uses of some immediates into copies (llvm#154757)
In some cases this will require an avoidable re-defining of a register, but it works out better most of the time. Also allow folding 64-bit immediates into subregister extracts, unless it would break an inline constant. We could be more aggressive here, but this set of conditions seems to do a reasonable job without introducing too many regressions.
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‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3554,13 +3554,12 @@ static unsigned getNewFMAMKInst(const GCNSubtarget &ST, unsigned Opc) {
35543554

35553555
bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
35563556
Register Reg, MachineRegisterInfo *MRI) const {
3557-
if (!MRI->hasOneNonDBGUse(Reg))
3558-
return false;
3559-
35603557
int64_t Imm;
35613558
if (!getConstValDefinedInReg(DefMI, Reg, Imm))
35623559
return false;
35633560

3561+
const bool HasMultipleUses = !MRI->hasOneNonDBGUse(Reg);
3562+
35643563
assert(!DefMI.getOperand(0).getSubReg() && "Expected SSA form");
35653564

35663565
unsigned Opc = UseMI.getOpcode();
@@ -3572,6 +3571,25 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
35723571

35733572
const TargetRegisterClass *DstRC = RI.getRegClassForReg(*MRI, DstReg);
35743573

3574+
if (HasMultipleUses) {
3575+
// TODO: This should fold in more cases with multiple use, but we need to
3576+
// more carefully consider what those uses are.
3577+
unsigned ImmDefSize = RI.getRegSizeInBits(*MRI->getRegClass(Reg));
3578+
3579+
// Avoid breaking up a 64-bit inline immediate into a subregister extract.
3580+
if (UseSubReg != AMDGPU::NoSubRegister && ImmDefSize == 64)
3581+
return false;
3582+
3583+
// Most of the time folding a 32-bit inline constant is free (though this
3584+
// might not be true if we can't later fold it into a real user).
3585+
//
3586+
// FIXME: This isInlineConstant check is imprecise if
3587+
// getConstValDefinedInReg handled the tricky non-mov cases.
3588+
if (ImmDefSize == 32 &&
3589+
!isInlineConstant(Imm, AMDGPU::OPERAND_REG_IMM_INT32))
3590+
return false;
3591+
}
3592+
35753593
bool Is16Bit = UseSubReg != AMDGPU::NoSubRegister &&
35763594
RI.getSubRegIdxSize(UseSubReg) == 16;
35773595

@@ -3659,6 +3677,9 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
36593677
return true;
36603678
}
36613679

3680+
if (HasMultipleUses)
3681+
return false;
3682+
36623683
if (Opc == AMDGPU::V_MAD_F32_e64 || Opc == AMDGPU::V_MAC_F32_e64 ||
36633684
Opc == AMDGPU::V_MAD_F16_e64 || Opc == AMDGPU::V_MAC_F16_e64 ||
36643685
Opc == AMDGPU::V_FMA_F32_e64 || Opc == AMDGPU::V_FMAC_F32_e64 ||

‎llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll‎

Lines changed: 27 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -3341,26 +3341,22 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
33413341
; CI-NEXT: v_or_b32_e32 v3, s3, v3
33423342
; CI-NEXT: .LBB13_16: ; %Flow50
33433343
; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[8:9], 0
3344-
; CI-NEXT: v_mov_b32_e32 v4, 0x7ff80000
3345-
; CI-NEXT: s_mov_b32 s2, 0
3346-
; CI-NEXT: s_mov_b32 s3, 0x7ff00000
3347-
; CI-NEXT: v_cndmask_b32_e64 v5, v0, 0, vcc
3348-
; CI-NEXT: v_cndmask_b32_e32 v6, v1, v4, vcc
3349-
; CI-NEXT: v_mov_b32_e32 v0, s4
3350-
; CI-NEXT: v_mov_b32_e32 v1, s5
3351-
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
3352-
; CI-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
3353-
; CI-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc
3354-
; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0
3355-
; CI-NEXT: v_cndmask_b32_e64 v5, v2, 0, vcc
3356-
; CI-NEXT: v_cndmask_b32_e32 v6, v3, v4, vcc
3357-
; CI-NEXT: v_mov_b32_e32 v2, s6
3358-
; CI-NEXT: v_mov_b32_e32 v3, s7
3359-
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[2:3]
3344+
; CI-NEXT: v_mov_b32_e32 v4, 0
3345+
; CI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
3346+
; CI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
33603347
; CI-NEXT: s_mov_b32 s2, -1
33613348
; CI-NEXT: s_mov_b32 s3, 0xf000
3362-
; CI-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
3363-
; CI-NEXT: v_cndmask_b32_e32 v3, v4, v6, vcc
3349+
; CI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
3350+
; CI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
3351+
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5]
3352+
; CI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
3353+
; CI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
3354+
; CI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0
3355+
; CI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
3356+
; CI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
3357+
; CI-NEXT: v_cmp_nge_f64_e64 vcc, |s[6:7]|, v[4:5]
3358+
; CI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
3359+
; CI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
33643360
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
33653361
; CI-NEXT: s_endpgm
33663362
;
@@ -3547,26 +3543,22 @@ define amdgpu_kernel void @frem_v2f64(ptr addrspace(1) %out, ptr addrspace(1) %i
35473543
; VI-NEXT: v_or_b32_e32 v3, s3, v3
35483544
; VI-NEXT: .LBB13_16: ; %Flow50
35493545
; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[8:9], 0
3550-
; VI-NEXT: v_mov_b32_e32 v4, 0x7ff80000
3551-
; VI-NEXT: s_mov_b32 s2, 0
3552-
; VI-NEXT: s_mov_b32 s3, 0x7ff00000
3553-
; VI-NEXT: v_cndmask_b32_e64 v5, v0, 0, vcc
3554-
; VI-NEXT: v_cndmask_b32_e32 v6, v1, v4, vcc
3555-
; VI-NEXT: v_mov_b32_e32 v0, s4
3556-
; VI-NEXT: v_mov_b32_e32 v1, s5
3557-
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[0:1]|, s[2:3]
3558-
; VI-NEXT: v_cndmask_b32_e32 v0, 0, v5, vcc
3559-
; VI-NEXT: v_cndmask_b32_e32 v1, v4, v6, vcc
3546+
; VI-NEXT: v_mov_b32_e32 v4, 0
3547+
; VI-NEXT: v_mov_b32_e32 v6, 0x7ff80000
3548+
; VI-NEXT: v_mov_b32_e32 v5, 0x7ff00000
3549+
; VI-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
3550+
; VI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
3551+
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[4:5]|, v[4:5]
3552+
; VI-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
3553+
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
35603554
; VI-NEXT: v_cmp_nlg_f64_e64 vcc, s[10:11], 0
3561-
; VI-NEXT: v_cndmask_b32_e64 v5, v2, 0, vcc
3562-
; VI-NEXT: v_cndmask_b32_e32 v6, v3, v4, vcc
3563-
; VI-NEXT: v_mov_b32_e32 v2, s6
3564-
; VI-NEXT: v_mov_b32_e32 v3, s7
3565-
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |v[2:3]|, s[2:3]
3566-
; VI-NEXT: v_cndmask_b32_e32 v2, 0, v5, vcc
3567-
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v6, vcc
3555+
; VI-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc
3556+
; VI-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc
3557+
; VI-NEXT: v_cmp_nge_f64_e64 vcc, |s[6:7]|, v[4:5]
35683558
; VI-NEXT: v_mov_b32_e32 v5, s1
35693559
; VI-NEXT: v_mov_b32_e32 v4, s0
3560+
; VI-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
3561+
; VI-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
35703562
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
35713563
; VI-NEXT: s_endpgm
35723564
%gep2 = getelementptr <2 x double>, ptr addrspace(1) %in2, i32 4

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -358,12 +358,12 @@ main_body:
358358
define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #0 {
359359
; GFX11-TRUE16-LABEL: v_interp_f16_imm_params:
360360
; GFX11-TRUE16: ; %bb.0: ; %main_body
361-
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
361+
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
362362
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
363-
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s1
363+
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, 0
364364
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
365365
; GFX11-TRUE16-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
366-
; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v2 wait_exp:7
366+
; GFX11-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v2, v3 wait_exp:7
367367
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
368368
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
369369
; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l
@@ -383,12 +383,12 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
383383
;
384384
; GFX12-TRUE16-LABEL: v_interp_f16_imm_params:
385385
; GFX12-TRUE16: ; %bb.0: ; %main_body
386-
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, 0
386+
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
387387
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
388-
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s1
388+
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
389389
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
390390
; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
391-
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v3, v2 wait_exp:7
391+
; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v2, v3 wait_exp:7
392392
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
393393
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
394394
; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.h, v0.l

‎llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll‎

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1379,45 +1379,43 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_vgpr_offset(ptr addrspace(1) in
13791379
; GFX6-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset:
13801380
; GFX6: ; %bb.0:
13811381
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1382-
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
1382+
; GFX6-NEXT: v_lshl_b64 v[1:2], v[0:1], 2
13831383
; GFX6-NEXT: s_mov_b32 s0, s2
13841384
; GFX6-NEXT: s_mov_b32 s1, s3
1385-
; GFX6-NEXT: v_mov_b32_e32 v2, 2
1385+
; GFX6-NEXT: v_mov_b32_e32 v0, 2
13861386
; GFX6-NEXT: s_mov_b32 s2, 0
13871387
; GFX6-NEXT: s_mov_b32 s3, 0xf000
1388-
; GFX6-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
1388+
; GFX6-NEXT: buffer_atomic_add v0, v[1:2], s[0:3], 0 addr64 glc
13891389
; GFX6-NEXT: s_waitcnt vmcnt(0)
13901390
; GFX6-NEXT: buffer_wbinvl1
1391-
; GFX6-NEXT: v_mov_b32_e32 v0, v2
13921391
; GFX6-NEXT: s_waitcnt expcnt(0)
13931392
; GFX6-NEXT: ; return to shader part epilog
13941393
;
13951394
; GFX7-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset:
13961395
; GFX7: ; %bb.0:
13971396
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
1398-
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
1397+
; GFX7-NEXT: v_lshl_b64 v[1:2], v[0:1], 2
13991398
; GFX7-NEXT: s_mov_b32 s0, s2
14001399
; GFX7-NEXT: s_mov_b32 s1, s3
1401-
; GFX7-NEXT: v_mov_b32_e32 v2, 2
1400+
; GFX7-NEXT: v_mov_b32_e32 v0, 2
14021401
; GFX7-NEXT: s_mov_b32 s2, 0
14031402
; GFX7-NEXT: s_mov_b32 s3, 0xf000
1404-
; GFX7-NEXT: buffer_atomic_add v2, v[0:1], s[0:3], 0 addr64 glc
1403+
; GFX7-NEXT: buffer_atomic_add v0, v[1:2], s[0:3], 0 addr64 glc
14051404
; GFX7-NEXT: s_waitcnt vmcnt(0)
14061405
; GFX7-NEXT: buffer_wbinvl1
1407-
; GFX7-NEXT: v_mov_b32_e32 v0, v2
14081406
; GFX7-NEXT: ; return to shader part epilog
14091407
;
14101408
; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset:
14111409
; GFX12: ; %bb.0:
14121410
; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0
14131411
; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
1414-
; GFX12-NEXT: v_mov_b32_e32 v4, 2
1415-
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
1412+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
14161413
; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1]
14171414
; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0
14181415
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
14191416
; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v3, v1, vcc_lo
1420-
; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v4, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
1417+
; GFX12-NEXT: v_mov_b32_e32 v2, 2
1418+
; GFX12-NEXT: global_atomic_add_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
14211419
; GFX12-NEXT: s_wait_loadcnt 0x0
14221420
; GFX12-NEXT: global_inv scope:SCOPE_DEV
14231421
; GFX12-NEXT: s_wait_loadcnt 0x0

‎llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll‎

Lines changed: 15 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -229,21 +229,23 @@ define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
229229
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
230230
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
231231
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
232-
; GFX6-NEXT: v_min_i32_e32 v5, 0, v0
232+
; GFX6-NEXT: v_min_i32_e32 v6, 0, v0
233+
; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
233234
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
234235
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
235236
; GFX6-NEXT: v_max_i32_e32 v4, 0, v0
236-
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, 0x80000000, v5
237+
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v7, v6
237238
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x7fffffff, v4
238-
; GFX6-NEXT: v_max_i32_e32 v1, v5, v1
239+
; GFX6-NEXT: v_max_i32_e32 v1, v6, v1
239240
; GFX6-NEXT: v_min_i32_e32 v1, v1, v4
240241
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1
241242
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
242243
; GFX6-NEXT: v_min_i32_e32 v4, 0, v1
244+
; GFX6-NEXT: v_bfrev_b32_e32 v5, -2
243245
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
244246
; GFX6-NEXT: v_max_i32_e32 v3, 0, v1
245247
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 0x80000000, v4
246-
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x7fffffff, v3
248+
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v5, v3
247249
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
248250
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
249251
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2
@@ -2951,20 +2953,22 @@ define amdgpu_ps float @saddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
29512953
; GFX6-LABEL: saddsat_v2i16_vs:
29522954
; GFX6: ; %bb.0:
29532955
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
2954-
; GFX6-NEXT: v_min_i32_e32 v3, 0, v0
2956+
; GFX6-NEXT: v_min_i32_e32 v4, 0, v0
2957+
; GFX6-NEXT: v_bfrev_b32_e32 v5, 1
29552958
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
29562959
; GFX6-NEXT: v_max_i32_e32 v2, 0, v0
2957-
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
2960+
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v5, v4
29582961
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
2959-
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
2962+
; GFX6-NEXT: v_max_i32_e32 v4, s0, v4
2963+
; GFX6-NEXT: v_min_i32_e32 v2, v4, v2
29602964
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
2961-
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
2962-
; GFX6-NEXT: v_min_i32_e32 v3, 0, v1
2965+
; GFX6-NEXT: v_bfrev_b32_e32 v3, -2
29632966
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
2964-
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
29652967
; GFX6-NEXT: v_max_i32_e32 v2, 0, v1
2968+
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v3, v2
2969+
; GFX6-NEXT: v_min_i32_e32 v3, 0, v1
2970+
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
29662971
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, 0x80000000, v3
2967-
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, 0x7fffffff, v2
29682972
; GFX6-NEXT: v_max_i32_e32 v3, s0, v3
29692973
; GFX6-NEXT: v_min_i32_e32 v2, v3, v2
29702974
; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2

‎llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1067,24 +1067,24 @@ define i64 @v_srem_i64_pow2k_denom(i64 %num) {
10671067
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
10681068
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
10691069
; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[1:2]
1070-
; CHECK-NEXT: v_sub_i32_e64 v0, s[4:5], v4, v0
1071-
; CHECK-NEXT: v_subb_u32_e64 v2, vcc, v9, v1, s[4:5]
1072-
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v9, v1
1073-
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
1074-
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
1075-
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
1076-
; CHECK-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
1070+
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
1071+
; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
1072+
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1
1073+
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
10771074
; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v5
1078-
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
10791075
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
10801076
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v5
1081-
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
1077+
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
10821078
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
1083-
; CHECK-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
1084-
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, 0x1000, v4
1079+
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v5
1080+
; CHECK-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
1081+
; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v4, v5
1082+
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
1083+
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2
10851084
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
1086-
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
1087-
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
1085+
; CHECK-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[4:5]
1086+
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
1087+
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
10881088
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
10891089
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
10901090
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
@@ -1660,24 +1660,24 @@ define i64 @v_srem_i64_oddk_denom(i64 %num) {
16601660
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
16611661
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v7, v2
16621662
; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v5, v2, v[1:2]
1663-
; CHECK-NEXT: v_sub_i32_e64 v0, s[4:5], v4, v0
1664-
; CHECK-NEXT: v_subb_u32_e64 v2, vcc, v9, v1, s[4:5]
1665-
; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v9, v1
1666-
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v5
1667-
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
1668-
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
1669-
; CHECK-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc
1663+
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
1664+
; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
1665+
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1
1666+
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
16701667
; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v5
1671-
; CHECK-NEXT: v_subbrev_u32_e64 v1, s[4:5], 0, v1, s[4:5]
16721668
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
16731669
; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v5
1674-
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
1670+
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
16751671
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
1676-
; CHECK-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
1677-
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, 0x12d8fb, v4
1672+
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v5
1673+
; CHECK-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
1674+
; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v4, v5
1675+
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
1676+
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2
16781677
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
1679-
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
1680-
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
1678+
; CHECK-NEXT: v_cndmask_b32_e64 v3, -1, v3, s[4:5]
1679+
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
1680+
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
16811681
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
16821682
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
16831683
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc

‎llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -233,16 +233,17 @@ define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
233233
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
234234
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
235235
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
236-
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
237-
; GFX6-NEXT: v_bfrev_b32_e32 v6, 1
238-
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
236+
; GFX6-NEXT: v_min_i32_e32 v6, -1, v0
237+
; GFX6-NEXT: v_bfrev_b32_e32 v7, 1
238+
; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7
239239
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
240-
; GFX6-NEXT: v_min_i32_e32 v1, v1, v5
240+
; GFX6-NEXT: v_min_i32_e32 v1, v1, v6
241241
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
242242
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
243+
; GFX6-NEXT: v_mov_b32_e32 v5, 0x80000001
243244
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
244245
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
245-
; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000001, v3
246+
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5
246247
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
247248
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000000, v4
248249
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
@@ -1260,7 +1261,8 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
12601261
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
12611262
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4
12621263
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
1263-
; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000000, v5
1264+
; GFX6-NEXT: v_bfrev_b32_e32 v6, 1
1265+
; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v6
12641266
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
12651267
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
12661268
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
@@ -1279,7 +1281,8 @@ define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
12791281
; GFX8-NEXT: v_max_i32_e32 v4, -1, v0
12801282
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000001, v4
12811283
; GFX8-NEXT: v_min_i32_e32 v5, -1, v0
1282-
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000000, v5
1284+
; GFX8-NEXT: v_bfrev_b32_e32 v6, 1
1285+
; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v6
12831286
; GFX8-NEXT: v_max_i32_e32 v2, v4, v2
12841287
; GFX8-NEXT: v_min_i32_e32 v2, v2, v5
12851288
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2

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