Add open-source FPGA cores (OpenFPGA/SOFA)

[romangauchi]

Hello,

I am part of the LNIS research lab at the University of Utah (Github, Website), which has developed OpenFPGA - an automatic IP generator for customizable FPGA architectures (Github).
FuseSoC seems to be an excellent opportunity to integrate hard-IP FPGA cores as hardware accelerators. Also, we built 3 open-source FPGA cores using the Google Skywater PDK (SOFA), with all the features listed below.
Following the fusesoc-cores documentation, I have described each FPGA core as a FuseSoC's core that can be integrated into a future multi-IP systems.

Thanks for reviewing my application, and please let me know if anything is wrong!

• SOFA_CHD: Skywater Open-source FpgA (SOFA) - Custom High-Density Design

  • Open-source 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture (documentation, github)
  • Designed with Google Skywater 130nm PDK with HD standard cell library + Custom Transmission Gate Cells
  • Base K4 architecture from VPR with 60 vertical and horizontal channels
  • Fabricated with eFabless Open MPW-one shuttle program (slot-039)

• SOFA_HD: Skywater Open-source FpgA (SOFA) - High-Density Design

  • Open-source 12x12 FPGA (documentation, github)
  • Designed with Google Skywater 130nm PDK with HD standard cell library
  • Base K4 architecture from VPR with 40 vertical and horizontal channels
  • No adders (carry-chain) or flipflop reset pins
  • Fabricated with eFabless Open MPW-one shuttle program (slot-017)

• SOFA_QLHD: Skywater Open-source FpgA (SOFA) - QuickLogic' soft-adder High-Density Design

  • Opensource 12x12 FPGA with adapted QuickLogic' soft-adder CLB architecture (documentation, github)
  • Designed with Skywater130nm PDK with HD standard cell library
  • Base K4 architecture from VPR with 60 vertical and horizontal channels
  • Fabricated with eFabless Open MPW-one shuttle program (slot-036)

Cheers!