Feature/open logic fix

open-logic/olo_axi.core

@@ -6,11 +6,11 @@ description : AXI related modules see https://github.com/open-logic/open-logic/b
 filesets:
   rtl:
     files:
-      - vhdl/olo_axi_master_simple.vhd
-      - vhdl/olo_axi_pl_stage.vhd
-      - vhdl/olo_axi_master_full.vhd
-      - vhdl/olo_axi_lite_slave.vhd
-      - vhdl/olo_axi_pkg_protocol.vhd
+      - src/axi/vhdl/olo_axi_master_simple.vhd
+      - src/axi/vhdl/olo_axi_pl_stage.vhd
+      - src/axi/vhdl/olo_axi_master_full.vhd
+      - src/axi/vhdl/olo_axi_lite_slave.vhd
+      - src/axi/vhdl/olo_axi_pkg_protocol.vhd
     file_type : vhdlSource
     logical_name : olo
     depend :

open-logic/olo_base.core

@@ -6,39 +6,39 @@ description : Basic Circuitry (e.g. FIFOs, CDCs, ...) see https://github.com/ope
 filesets:
   rtl:
     files:
-      - vhdl/olo_base_cc_n2xn.vhd
-      - vhdl/olo_base_arb_rr.vhd
-      - vhdl/olo_base_cc_simple.vhd
-      - vhdl/olo_base_ram_sdp.vhd
-      - vhdl/olo_base_delay_cfg.vhd
-      - vhdl/olo_base_decode_firstbit.vhd
-      - vhdl/olo_base_ram_tdp.vhd
-      - vhdl/olo_base_strobe_gen.vhd
-      - vhdl/olo_base_wconv_n2xn.vhd
-      - vhdl/olo_base_fifo_async.vhd
-      - vhdl/olo_base_arb_prio.vhd
-      - vhdl/olo_base_cc_reset.vhd
-      - vhdl/olo_base_delay.vhd
-      - vhdl/olo_base_prbs.vhd
-      - vhdl/olo_base_tdm_mux.vhd
-      - vhdl/olo_base_cc_handshake.vhd
-      - vhdl/olo_base_pkg_array.vhd
-      - vhdl/olo_base_flowctrl_handler.vhd
-      - vhdl/olo_base_dyn_sft.vhd
-      - vhdl/olo_base_strobe_div.vhd
-      - vhdl/olo_base_ram_sp.vhd
-      - vhdl/olo_base_fifo_sync.vhd
-      - vhdl/olo_base_cc_pulse.vhd
-      - vhdl/olo_base_pkg_logic.vhd
-      - vhdl/olo_base_cam.vhd
-      - vhdl/olo_base_cc_status.vhd
-      - vhdl/olo_base_reset_gen.vhd
-      - vhdl/olo_base_pkg_math.vhd
-      - vhdl/olo_base_wconv_xn2n.vhd
-      - vhdl/olo_base_fifo_packet.vhd
-      - vhdl/olo_base_pl_stage.vhd
-      - vhdl/olo_base_cc_bits.vhd
-      - vhdl/olo_base_cc_xn2n.vhd
+      - src/base/vhdl/olo_base_cc_n2xn.vhd
+      - src/base/vhdl/olo_base_arb_rr.vhd
+      - src/base/vhdl/olo_base_cc_simple.vhd
+      - src/base/vhdl/olo_base_ram_sdp.vhd
+      - src/base/vhdl/olo_base_delay_cfg.vhd
+      - src/base/vhdl/olo_base_decode_firstbit.vhd
+      - src/base/vhdl/olo_base_ram_tdp.vhd
+      - src/base/vhdl/olo_base_strobe_gen.vhd
+      - src/base/vhdl/olo_base_wconv_n2xn.vhd
+      - src/base/vhdl/olo_base_fifo_async.vhd
+      - src/base/vhdl/olo_base_arb_prio.vhd
+      - src/base/vhdl/olo_base_cc_reset.vhd
+      - src/base/vhdl/olo_base_delay.vhd
+      - src/base/vhdl/olo_base_prbs.vhd
+      - src/base/vhdl/olo_base_tdm_mux.vhd
+      - src/base/vhdl/olo_base_cc_handshake.vhd
+      - src/base/vhdl/olo_base_pkg_array.vhd
+      - src/base/vhdl/olo_base_flowctrl_handler.vhd
+      - src/base/vhdl/olo_base_dyn_sft.vhd
+      - src/base/vhdl/olo_base_strobe_div.vhd
+      - src/base/vhdl/olo_base_ram_sp.vhd
+      - src/base/vhdl/olo_base_fifo_sync.vhd
+      - src/base/vhdl/olo_base_cc_pulse.vhd
+      - src/base/vhdl/olo_base_pkg_logic.vhd
+      - src/base/vhdl/olo_base_cam.vhd
+      - src/base/vhdl/olo_base_cc_status.vhd
+      - src/base/vhdl/olo_base_reset_gen.vhd
+      - src/base/vhdl/olo_base_pkg_math.vhd
+      - src/base/vhdl/olo_base_wconv_xn2n.vhd
+      - src/base/vhdl/olo_base_fifo_packet.vhd
+      - src/base/vhdl/olo_base_pl_stage.vhd
+      - src/base/vhdl/olo_base_cc_bits.vhd
+      - src/base/vhdl/olo_base_cc_xn2n.vhd
     file_type : vhdlSource
     logical_name : olo
 

open-logic/olo_intf.core

@@ -6,13 +6,13 @@ description : Interfaces (e.g. I2C, synchronizer, SPI, ...) see https://github.c
 filesets:
   rtl:
     files:
-      - vhdl/olo_intf_spi_slave.vhd
-      - vhdl/olo_intf_i2c_master.vhd
-      - vhdl/olo_intf_debounce.vhd
-      - vhdl/olo_intf_clk_meas.vhd
-      - vhdl/olo_intf_spi_master.vhd
-      - vhdl/olo_intf_sync.vhd
-      - vhdl/olo_intf_uart.vhd
+      - src/intf/vhdl/olo_intf_spi_slave.vhd
+      - src/intf/vhdl/olo_intf_i2c_master.vhd
+      - src/intf/vhdl/olo_intf_debounce.vhd
+      - src/intf/vhdl/olo_intf_clk_meas.vhd
+      - src/intf/vhdl/olo_intf_spi_master.vhd
+      - src/intf/vhdl/olo_intf_sync.vhd
+      - src/intf/vhdl/olo_intf_uart.vhd
     file_type : vhdlSource
     logical_name : olo
     depend :

open-logic/olo_quartus_tutorial.core

@@ -6,11 +6,11 @@ filesets:
 
   de0_cv:
     files:
-      - timing.sdc  : {file_type : SDC}
-      - pinout.tcl  : {file_type : tclSource}
+      - doc/tutorials/QuartusTutorial/Files/timing.sdc  : {file_type : SDC}
+      - doc/tutorials/QuartusTutorial/Files/pinout.tcl  : {file_type : tclSource}
 
   rtl:
-    files: [quartus_tutorial.vhd : {file_type : vhdlSource}]
+    files: [doc/tutorials/QuartusTutorial/Files/quartus_tutorial.vhd : {file_type : vhdlSource}]
     depend :
       - "open-logic:open-logic:base"
       - "open-logic:open-logic:intf"

open-logic/olo_vivado_tutorial.core

@@ -6,11 +6,11 @@ filesets:
 
   zybo_z7:
     files:
-      - vivado_tutorial.vhd : {file_type : vhdlSource}
-      - pinout.xdc : {file_type : xdc}
+      - doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource}
+      - doc/tutorials/VivadoTutorial/Files/pinout.xdc : {file_type : xdc}
 
   rtl:
-    files: [vivado_tutorial.vhd : {file_type : vhdlSource}]
+    files: [doc/tutorials/VivadoTutorial/Files/vivado_tutorial.vhd : {file_type : vhdlSource}]
     depend :
       - "open-logic:open-logic:base"
       - "open-logic:open-logic:intf"