Questions on Compatibility and Clock Tree Embedding for OpenFPGA Tile-Based Architectures

[AhmadHouraniah]

Hi,
I'm currently exploring the use of this flow to generate and embed a clock tree into our OpenFPGA-based architecture, and I had a few questions regarding compatibility and setup:

1. Is the repository currently in a functional state with regards to clock tree embedding?

• I'm hoping to use it end-to-end for clock tree embedding. Could you confirm if the current implementation is expected to work out for different architectures?

2. Does it support tile-based architectures from OpenFPGA?

• We're working with a tile-based architecture and want to understand whether this setup is supported directly, or if modifications would be required to integrate the clock tree generation properly.

3. Which version of SpyDrNet are supported by this repo?

• I’ve tried running the example examples/OpenFPGA_clock_tree/04_embed_clock_tree.py with multiple versions of spydrnet, but ran into different errors based on the version of spydrnet used such as:
  AttributeError: module 'spydrnet' has no attribute 'enable_file_logging'
TypeError: compose() got an unexpected keyword argument 'skip_constraints'

• These seem to point to version mismatches between spydrnet and spydrnet-physical. Could you clarify which versions are compatible with the repo? If there's a specific commit or release known to work, that would also be helpful.

I appreciate your time, and thanks again for making this project available!

Best regards,
Ahmad