Skip to content

Commit 9cc0401

Browse files
ISSOtmISSOtm
authored
Switch "CPU instruction set" to document encoding instead (#511)
1 parent 6af9e01 commit 9cc0401

File tree

1 file changed

+190
-149
lines changed

1 file changed

+190
-149
lines changed

‎src/CPU_Instruction_Set.md

Lines changed: 190 additions & 149 deletions
Original file line numberDiff line numberDiff line change
@@ -1,151 +1,192 @@
11
# CPU Instruction Set
22

3-
Tables below specify the mnemonic, encoding, clock cycles, affected
4-
flags (ordered as znhc), and description. The timings assume a CPU
5-
clock frequency of 4.194304 MHz (or 8.4 MHz for CGB in double speed
6-
mode), called "T-states". Because all Game Boy timings are divisible
7-
by 4, many people specify timings and clock frequency divided by 4,
8-
called "M-cycles".
9-
10-
## 8-bit Load instructions
11-
12-
Mnemonic | Encoding | Clock cycles | Flags | Description
13-
-----------------|----------|--------------|-------|-------------
14-
ld r,r | xx | 4 | ---- | r=r
15-
ld r,n | xx nn | 8 | ---- | r=n
16-
ld r,(HL) | xx | 8 | ---- | r=(HL)
17-
ld (HL),r | 7x | 8 | ---- | (HL)=r
18-
ld (HL),n | 36 nn | 12 | ---- | (HL)=n
19-
ld A,(BC) | 0A | 8 | ---- | A=(BC)
20-
ld A,(DE) | 1A | 8 | ---- | A=(DE)
21-
ld A,(nn) | FA | 16 | ---- | A=(nn)
22-
ld (BC),A | 02 | 8 | ---- | (BC)=A
23-
ld (DE),A | 12 | 8 | ---- | (DE)=A
24-
ld (nn),A | EA | 16 | ---- | (nn)=A
25-
ld A,(FF00+n) | F0 nn | 12 | ---- | read from io-port n (memory FF00+n)
26-
ld (FF00+n),A | E0 nn | 12 | ---- | write to io-port n (memory FF00+n)
27-
ld A,(FF00+C) | F2 | 8 | ---- | read from io-port C (memory FF00+C)
28-
ld (FF00+C),A | E2 | 8 | ---- | write to io-port C (memory FF00+C)
29-
ldi (HL),A | 22 | 8 | ---- | (HL)=A, HL=HL+1
30-
ldi A,(HL) | 2A | 8 | ---- | A=(HL), HL=HL+1
31-
ldd (HL),A | 32 | 8 | ---- | (HL)=A, HL=HL-1
32-
ldd A,(HL) | 3A | 8 | ---- | A=(HL), HL=HL-1
33-
34-
## 16-bit Load instructions
35-
36-
Mnemonic | Encoding | Clock cycles | Flags | Description
37-
-----------------|----------|--------------|-------|-------------
38-
ld rr,nn | x1 nn nn | 12 | ---- | rr=nn (rr may be BC,DE,HL or SP)
39-
ld (nn),SP | 08 nn nn | 20 | ---- | (nn)=SP
40-
ld SP,HL | F9 | 8 | ---- | SP=HL
41-
push rr | x5 | 16 | ---- | SP=SP-2 (SP)=rr ; rr may be BC,DE,HL,AF
42-
pop rr | x1 | 12 | (AF) | rr=(SP) SP=SP+2 ; rr may be BC,DE,HL,AF
43-
44-
## 8-bit Arithmetic/Logic instructions
45-
46-
Mnemonic | Encoding | Clock cycles | Flags | Description
47-
-----------------|----------|--------------|-------|-------------
48-
add A,r | 8x | 4 | z0hc | A=A+r
49-
add A,n | C6 nn | 8 | z0hc | A=A+n
50-
add A,(HL) | 86 | 8 | z0hc | A=A+(HL)
51-
adc A,r | 8x | 4 | z0hc | A=A+r+cy
52-
adc A,n | CE nn | 8 | z0hc | A=A+n+cy
53-
adc A,(HL) | 8E | 8 | z0hc | A=A+(HL)+cy
54-
sub r | 9x | 4 | z1hc | A=A-r
55-
sub n | D6 nn | 8 | z1hc | A=A-n
56-
sub (HL) | 96 | 8 | z1hc | A=A-(HL)
57-
sbc A,r | 9x | 4 | z1hc | A=A-r-cy
58-
sbc A,n | DE nn | 8 | z1hc | A=A-n-cy
59-
sbc A,(HL) | 9E | 8 | z1hc | A=A-(HL)-cy
60-
and r | Ax | 4 | z010 | A=A & r
61-
and n | E6 nn | 8 | z010 | A=A & n
62-
and (HL) | A6 | 8 | z010 | A=A & (HL)
63-
xor r | Ax | 4 | z000 | A=A xor r
64-
xor n | EE nn | 8 | z000 | A=A xor n
65-
xor (HL) | AE | 8 | z000 | A=A xor (HL)
66-
or r | Bx | 4 | z000 | A=A \| r
67-
or n | F6 nn | 8 | z000 | A=A \| n
68-
or (HL) | B6 | 8 | z000 | A=A \| (HL)
69-
cp r | Bx | 4 | z1hc | compare A-r
70-
cp n | FE nn | 8 | z1hc | compare A-n
71-
cp (HL) | BE | 8 | z1hc | compare A-(HL)
72-
inc r | xx | 4 | z0h- | r=r+1
73-
inc (HL) | 34 | 12 | z0h- | (HL)=(HL)+1
74-
dec r | xx | 4 | z1h- | r=r-1
75-
dec (HL) | 35 | 12 | z1h- | (HL)=(HL)-1
76-
daa | 27 | 4 | z-0c | decimal adjust A
77-
cpl | 2F | 4 | -11- | A = A xor FF
78-
79-
## 16-bit Arithmetic/Logic instructions
80-
81-
Mnemonic | Encoding | Clock cycles | Flags | Description
82-
-----------------|----------|--------------|-------|-------------
83-
add HL,rr | x9 | 8 | -0hc | HL = HL+rr ; rr may be BC,DE,HL,SP
84-
inc rr | x3 | 8 | ---- | rr = rr+1 ; rr may be BC,DE,HL,SP
85-
dec rr | xB | 8 | ---- | rr = rr-1 ; rr may be BC,DE,HL,SP
86-
add SP,dd | E8 dd | 16 | 00hc | SP = SP +/- dd ; dd is 8-bit signed number
87-
ld HL,SP+dd | F8 dd | 12 | 00hc | HL = SP +/- dd ; dd is 8-bit signed number
88-
89-
## Rotate and Shift instructions
90-
91-
Mnemonic | Encoding | Clock cycles | Flags | Description
92-
-----------------|----------|--------------|-------|-------------
93-
rlca | 07 | 4 | 000c | rotate A left
94-
rla | 17 | 4 | 000c | rotate A left through carry
95-
rrca | 0F | 4 | 000c | rotate A right
96-
rra | 1F | 4 | 000c | rotate A right through carry
97-
rlc r | CB 0x | 8 | z00c | rotate left
98-
rlc (HL) | CB 06 | 16 | z00c | rotate left
99-
rl r | CB 1x | 8 | z00c | rotate left through carry
100-
rl (HL) | CB 16 | 16 | z00c | rotate left through carry
101-
rrc r | CB 0x | 8 | z00c | rotate right
102-
rrc (HL) | CB 0E | 16 | z00c | rotate right
103-
rr r | CB 1x | 8 | z00c | rotate right through carry
104-
rr (HL) | CB 1E | 16 | z00c | rotate right through carry
105-
sla r | CB 2x | 8 | z00c | shift left arithmetic (b0=0)
106-
sla (HL) | CB 26 | 16 | z00c | shift left arithmetic (b0=0)
107-
swap r | CB 3x | 8 | z000 | exchange low/hi-nibble
108-
swap (HL) | CB 36 | 16 | z000 | exchange low/hi-nibble
109-
sra r | CB 2x | 8 | z00c | shift right arithmetic (b7=b7)
110-
sra (HL) | CB 2E | 16 | z00c | shift right arithmetic (b7=b7)
111-
srl r | CB 3x | 8 | z00c | shift right logical (b7=0)
112-
srl (HL) | CB 3E | 16 | z00c | shift right logical (b7=0)
113-
114-
## Single-bit Operation instructions
115-
116-
Mnemonic | Encoding | Clock cycles | Flags | Description
117-
-----------------|----------|--------------|-------|-------------
118-
bit n,r | CB xx | 8 | z01- | test bit n
119-
bit n,(HL) | CB xx | 12 | z01- | test bit n
120-
set n,r | CB xx | 8 | ---- | set bit n
121-
set n,(HL) | CB xx | 16 | ---- | set bit n
122-
res n,r | CB xx | 8 | ---- | reset bit n
123-
res n,(HL) | CB xx | 16 | ---- | reset bit n
124-
125-
## CPU Control instructions
126-
127-
Mnemonic | Encoding | Clock cycles | Flags | Description
128-
-----------------|----------|--------------|-------|-------------
129-
ccf | 3F | 4 | -00c | cy=cy xor 1
130-
scf | 37 | 4 | -001 | cy=1
131-
nop | 00 | 4 | ---- | no operation
132-
halt | 76 | N*4 | ---- | halt until interrupt occurs (low power)
133-
stop | 10 00 | ? | ---- | low power standby mode (VERY low power)
134-
di | F3 | 4 | ---- | disable interrupts, IME=0
135-
ei | FB | 4 | ---- | enable interrupts, IME=1
136-
137-
## Jump instructions
138-
139-
Mnemonic | Encoding | Clock cycles | Flags | Description
140-
-----------------|----------|--------------|-------|-------------
141-
jp nn | C3 nn nn | 16 | ---- | jump to nn, PC=nn
142-
jp HL | E9 | 4 | ---- | jump to HL, PC=HL
143-
jp f,nn | xx nn nn | 16/12 | ---- | conditional jump if nz,z,nc,c
144-
jr PC+dd | 18 dd | 12 | ---- | relative jump to nn (PC=PC+8-bit signed)
145-
jr f,PC+dd | xx dd | 12/8 | ---- | conditional relative jump if nz,z,nc,c
146-
call nn | CD nn nn | 24 | ---- | call to nn, SP=SP-2, (SP)=PC, PC=nn
147-
call f,nn | xx nn nn | 24/12 | ---- | conditional call if nz,z,nc,c
148-
ret | C9 | 16 | ---- | return, PC=(SP), SP=SP+2
149-
ret f | xx | 20/8 | ---- | conditional return if nz,z,nc,c
150-
reti | D9 | 16 | ---- | return and enable interrupts (IME=1)
151-
rst n | xx | 16 | ---- | call to 00,08,10,18,20,28,30,38
3+
:::tip
4+
5+
If you are looking for textual explanations of what each each instruction does, please read [gbz80(7)](http://rgbds.gbdev.io/docs/gbz80.7); if you want a compact reference card/cheat sheet of each opcode and its flag effects, please consult [the optables](http://gbdev.io/gb-opcodes/optables) (whose [octal view](http://gbdev.io/gb-opcodes/optables/octal) makes most encoding patterns more apparent).
6+
7+
:::
8+
9+
<style>table td { padding: 3px 10px; overflow-wrap: break-word; }</style>
10+
11+
The Game Boy's SM83 processor possesses a <abbr title="Complex Instruction Set Computer">CISC</abbr>, variable-length instruction set.
12+
This page attempts to shed some light on how the CPU decodes the raw bytes fed into it into instructions.
13+
14+
The first byte of each instruction is typically called the "opcode" (for "operation code").
15+
By noticing that some instructions perform identical operations but with different parameters, they can be grouped together; for example, `inc bc`, `inc de`, `inc hl`, and `inc sp` differ only in what 16-bit register they modify.
16+
17+
In each table, one line represents one such grouping.
18+
Since many groupings have some variation, the variation has to be encoded in the instruction; for example, the above four instructions will be collectively referred to as `inc r16`.
19+
Here are the possible placeholders and their values:
20+
21+
{{#bits 8 <
22+
"r8" 0:"<code>b</code>" 1:"<code>c</code>" 2:"<code>d</code>" 3:"<code>e</code>" 4:"<code>h</code>" 5:"<code>l</code>" 6:"<code>[hl]</code>" 7:"<code>a</code>" ;
23+
"r16" 0:"<code>bc</code>" 1:"<code>de</code>" 2:"<code>hl</code>" 3:"<code>sp</code>" ;
24+
"r16stk" 0:"<code>bc</code>" 1:"<code>de</code>" 2:"<code>hl</code>" 3:"<code>af</code>" ;
25+
"r16mem" 0:"<code>bc</code>" 1:"<code>de</code>" 2:"<code>hl+</code>" 3:"<code>hl-</code>" ;
26+
"cond" 0:"<code>nz</code>" 1:"<code>z</code>" 2:"<code>nc</code>" 3:"<code>c</code>" ;
27+
"b3" 0-7:"A 3-bit bit index" ;
28+
"tgt3" 0-7:"<code>rst</code>'s target address, divided by 8" ;
29+
"imm8" 0-7:"The following byte" ;
30+
"imm16" 0-7:"The following two bytes, in little-endian order" ;
31+
}}
32+
33+
These last two are a little special: if they are present in the instruction's mnemonic, it means that the instruction is 1 (`imm8`) / 2 (`imm16`) extra bytes long.
34+
35+
:::tip
36+
37+
`[hl+]` and `[hl-]` can also be notated `[hli]` and `[hld]` respectively (as in **i**ncrement and **d**ecrement).
38+
39+
:::
40+
41+
Groupings have been loosely associated based on what they do into separate tables; those have no particular ordering, and are purely for readability and convenience.
42+
Finally, the instruction "families" have been further grouped into four "blocks", differentiated by the first two bits of the opcode.
43+
44+
## Block 0
45+
46+
{{#bits 8 >
47+
"<code>nop</code>" 7:"0" 6:"0" 5:"0" 4:"0" 3:"0" 2:"0" 1:"0" 0:"0"
48+
}}
49+
50+
{{#bits 8 >
51+
"<code>ld r16, imm16</code>" 7:"0" 6:"0" 5-4:"Dest (r16)" 3:"0" 2:"0" 1:"0" 0:"1" ;
52+
"<code>ld [r16mem], a</code>" 7:"0" 6:"0" 5-4:"Dest (r16mem)" 3:"0" 2:"0" 1:"1" 0:"0" ;
53+
"<code>ld a, [r16mem]</code>" 7:"0" 6:"0" 5-4:"Source (r16mem)" 3:"1" 2:"0" 1:"1" 0:"0" ;
54+
"<code>ld [imm16], sp</code>" 7:"0" 6:"0" 5:"0" 4:"0" 3:"1" 2:"0" 1:"0" 0:"0" ;
55+
}}
56+
57+
{{#bits 8 >
58+
"<code>inc r16</code>" 7:"0" 6:"0" 5-4:"Operand (r16)" 3:"0" 2:"0" 1:"1" 0:"1" ;
59+
"<code>dec r16</code>" 7:"0" 6:"0" 5-4:"Operand (r16)" 3:"1" 2:"0" 1:"1" 0:"1" ;
60+
"<code>add hl, r16</code>" 7:"0" 6:"0" 5-4:"Operand (r16)" 3:"1" 2:"0" 1:"0" 0:"1" ;
61+
}}
62+
63+
{{#bits 8 >
64+
"<code>inc r8</code>" 7:"0" 6:"0" 5-3:"Operand (r8)" 2:"1" 1:"0" 0:"0" ;
65+
"<code>dec r8</code>" 7:"0" 6:"0" 5-3:"Operand (r8)" 2:"1" 1:"0" 0:"1" ;
66+
}}
67+
68+
{{#bits 8 >
69+
"<code>ld r8, imm8</code>" 7:"0" 6:"0" 5-3:"Dest (r8)" 2:"1" 1:"1" 0:"0"
70+
}}
71+
72+
{{#bits 8 >
73+
"<code>rlca</code>" 7:"0" 6:"0" 5:"0" 4:"0" 3:"0" 2:"1" 1:"1" 0:"1" ;
74+
"<code>rrca</code>" 7:"0" 6:"0" 5:"0" 4:"0" 3:"1" 2:"1" 1:"1" 0:"1" ;
75+
"<code>rla</code>" 7:"0" 6:"0" 5:"0" 4:"1" 3:"0" 2:"1" 1:"1" 0:"1" ;
76+
"<code>rra</code>" 7:"0" 6:"0" 5:"0" 4:"1" 3:"1" 2:"1" 1:"1" 0:"1" ;
77+
"<code>daa</code>" 7:"0" 6:"0" 5:"1" 4:"0" 3:"0" 2:"1" 1:"1" 0:"1" ;
78+
"<code>cpl</code>" 7:"0" 6:"0" 5:"1" 4:"0" 3:"1" 2:"1" 1:"1" 0:"1" ;
79+
"<code>scf</code>" 7:"0" 6:"0" 5:"1" 4:"1" 3:"0" 2:"1" 1:"1" 0:"1" ;
80+
"<code>ccf</code>" 7:"0" 6:"0" 5:"1" 4:"1" 3:"1" 2:"1" 1:"1" 0:"1" ;
81+
}}
82+
83+
{{#bits 8 >
84+
"<code>jr imm8</code>" 7:"0" 6:"0" 5:"0" 4:"1" 3:"1" 2:"0" 1:"0" 0:"0" ;
85+
"<code>jr cond, imm8</code>" 7:"0" 6:"0" 5:"1" 4-3:"Condition (cond)" 2:"0" 1:"0" 0:"0" ;
86+
}}
87+
88+
{{#bits 8 >
89+
"<code>stop</code>" 7:"0" 6:"0" 5:"0" 4:"1" 3:"0" 2:"0" 1:"0" 0:"0"
90+
}}
91+
92+
[`stop`](<#Using the STOP Instruction>) is often considered a **two-byte** instruction, though [the second byte is not always ignored](https://gist.github.com/SonoSooS/c0055300670d678b5ae8433e20bea595#nop-and-stop).
93+
94+
## Block 1: 8-bit register-to-register loads
95+
96+
{{#bits 8 >
97+
"<code>ld r8, r8</code>" 7:"0" 6:"1" 5-3:"Dest (r8)" 2-0:"Source (r8)"
98+
}}
99+
100+
**Exception**: trying to encode `ld [hl], [hl]` instead yields [the `halt` instruction](<#halt>):
101+
102+
{{#bits 8 >
103+
"<code>halt</code>" 7:"0" 6:"1" 5:"1" 4:"1" 3:"0" 2:"1" 1:"1" 0:"0"
104+
}}
105+
106+
## Block 2: 8-bit arithmetic
107+
108+
{{#bits 8 >
109+
"<code>add a, r8</code>" 7:"1" 6:"0" 5:"0" 4:"0" 3:"0" 2-0:"Operand (r8)" ;
110+
"<code>adc a, r8</code>" 7:"1" 6:"0" 5:"0" 4:"0" 3:"1" 2-0:"Operand (r8)" ;
111+
"<code>sub a, r8</code>" 7:"1" 6:"0" 5:"0" 4:"1" 3:"0" 2-0:"Operand (r8)" ;
112+
"<code>sbc a, r8</code>" 7:"1" 6:"0" 5:"0" 4:"1" 3:"1" 2-0:"Operand (r8)" ;
113+
"<code>and a, r8</code>" 7:"1" 6:"0" 5:"1" 4:"0" 3:"0" 2-0:"Operand (r8)" ;
114+
"<code>xor a, r8</code>" 7:"1" 6:"0" 5:"1" 4:"0" 3:"1" 2-0:"Operand (r8)" ;
115+
"<code>or a, r8</code>" 7:"1" 6:"0" 5:"1" 4:"1" 3:"0" 2-0:"Operand (r8)" ;
116+
"<code>cp a, r8</code>" 7:"1" 6:"0" 5:"1" 4:"1" 3:"1" 2-0:"Operand (r8)" ;
117+
}}
118+
119+
## Block 3
120+
121+
{{#bits 8 >
122+
"<code>add a, imm8</code>" 7:"1" 6:"1" 5:"0" 4:"0" 3:"0" 2:"1" 1:"1" 0:"0" ;
123+
"<code>adc a, imm8</code>" 7:"1" 6:"1" 5:"0" 4:"0" 3:"1" 2:"1" 1:"1" 0:"0" ;
124+
"<code>sub a, imm8</code>" 7:"1" 6:"1" 5:"0" 4:"1" 3:"0" 2:"1" 1:"1" 0:"0" ;
125+
"<code>sbc a, imm8</code>" 7:"1" 6:"1" 5:"0" 4:"1" 3:"1" 2:"1" 1:"1" 0:"0" ;
126+
"<code>and a, imm8</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"0" 2:"1" 1:"1" 0:"0" ;
127+
"<code>xor a, imm8</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"1" 2:"1" 1:"1" 0:"0" ;
128+
"<code>or a, imm8</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"0" 2:"1" 1:"1" 0:"0" ;
129+
"<code>cp a, imm8</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"1" 2:"1" 1:"1" 0:"0" ;
130+
}}
131+
132+
{{#bits 8 >
133+
"<code>ret cond</code>" 7:"1" 6:"1" 5:"0" 4-3:"Condition (cond)" 2:"0" 1:"0" 0:"0" ;
134+
"<code>ret</code>" 7:"1" 6:"1" 5:"0" 4:"0" 3:"1" 2:"0" 1:"0" 0:"1" ;
135+
"<code>reti</code>" 7:"1" 6:"1" 5:"0" 4:"1" 3:"1" 2:"0" 1:"0" 0:"1" ;
136+
"<code>jp cond, imm16</code>" 7:"1" 6:"1" 5:"0" 4-3:"Condition (cond)" 2:"0" 1:"1" 0:"0" ;
137+
"<code>jp imm16</code>" 7:"1" 6:"1" 5:"0" 4:"0" 3:"0" 2:"0" 1:"1" 0:"1" ;
138+
"<code>jp hl</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"1" 2:"0" 1:"0" 0:"1" ;
139+
"<code>call cond, imm16</code>" 7:"1" 6:"1" 5:"0" 4-3:"Condition (cond)" 2:"1" 1:"0" 0:"0" ;
140+
"<code>call imm16</code>" 7:"1" 6:"1" 5:"0" 4:"0" 3:"1" 2:"1" 1:"0" 0:"1" ;
141+
"<code>rst tgt3</code>" 7:"1" 6:"1" 5-3:"Target (tgt3)" 2:"1" 1:"1" 0:"1" ;
142+
}}
143+
144+
{{#bits 8 >
145+
"<code>pop r16stk</code>" 7:"1" 6:"1" 5-4:"Register (r16stk)" 3:"0" 2:"0" 1:"0" 0:"1" ;
146+
"<code>push r16stk</code>" 7:"1" 6:"1" 5-4:"Register (r16stk)" 3:"0" 2:"1" 1:"0" 0:"1" ;
147+
}}
148+
149+
{{#bits 8 >
150+
"Prefix (see block below)" 7:"1" 6:"1" 5:"0" 4:"0" 3:"1" 2:"0" 1:"1" 0:"1"
151+
}}
152+
153+
{{#bits 8 >
154+
"<code>ldh [c], a</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"0" 2:"1" 1:"0" 0:"0" ;
155+
"<code>ldh [imm8], a</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"0" 2:"0" 1:"0" 0:"0" ;
156+
"<code>ld [imm16], a</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"1" 2:"1" 1:"0" 0:"0" ;
157+
"<code>ldh a, [c]</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"0" 2:"1" 1:"0" 0:"0" ;
158+
"<code>ldh a, [imm8]</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"0" 2:"0" 1:"0" 0:"0" ;
159+
"<code>ld a, [imm16]</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"1" 2:"1" 1:"0" 0:"0" ;
160+
}}
161+
162+
{{#bits 8 >
163+
"<code>add sp, imm8</code>" 7:"1" 6:"1" 5:"1" 4:"0" 3:"1" 2:"0" 1:"0" 0:"0" ;
164+
"<code>ld hl, sp + imm8</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"1" 2:"0" 1:"0" 0:"0" ;
165+
"<code>ld sp, hl</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"1" 2:"0" 1:"0" 0:"1" ;
166+
}}
167+
168+
{{#bits 8 >
169+
"<code>di</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"0" 2:"0" 1:"1" 0:"1" ;
170+
"<code>ei</code>" 7:"1" 6:"1" 5:"1" 4:"1" 3:"1" 2:"0" 1:"1" 0:"1" ;
171+
}}
172+
173+
The following opcodes are **invalid**, and [hard-lock the CPU](https://gist.github.com/SonoSooS/c0055300670d678b5ae8433e20bea595#opcode-holes-not-implemented-opcodes) until the console is powered off: \$D3, \$DB, \$DD, \$E3, \$E4, \$EB, \$EC, \$ED, \$F4, \$FC, and \$FD.
174+
175+
## \$CB prefix instructions
176+
177+
{{#bits 8 >
178+
"<code>rlc r8</code>" 7:"0" 6:"0" 5:"0" 4:"0" 3:"0" 2-0:"Operand (r8)" ;
179+
"<code>rrc r8</code>" 7:"0" 6:"0" 5:"0" 4:"0" 3:"1" 2-0:"Operand (r8)" ;
180+
"<code>rl r8</code>" 7:"0" 6:"0" 5:"0" 4:"1" 3:"0" 2-0:"Operand (r8)" ;
181+
"<code>rr r8</code>" 7:"0" 6:"0" 5:"0" 4:"1" 3:"1" 2-0:"Operand (r8)" ;
182+
"<code>sla r8</code>" 7:"0" 6:"0" 5:"1" 4:"0" 3:"0" 2-0:"Operand (r8)" ;
183+
"<code>sra r8</code>" 7:"0" 6:"0" 5:"1" 4:"0" 3:"1" 2-0:"Operand (r8)" ;
184+
"<code>swap r8</code>" 7:"0" 6:"0" 5:"1" 4:"1" 3:"0" 2-0:"Operand (r8)" ;
185+
"<code>srl r8</code>" 7:"0" 6:"0" 5:"1" 4:"1" 3:"1" 2-0:"Operand (r8)" ;
186+
}}
187+
188+
{{#bits 8 >
189+
"<code>bit b3, r8</code>" 7:"0" 6:"1" 5-3:"Bit index (b3)" 2-0:"Operand (r8)" ;
190+
"<code>res b3, r8</code>" 7:"1" 6:"0" 5-3:"Bit index (b3)" 2-0:"Operand (r8)" ;
191+
"<code>set b3, r8</code>" 7:"1" 6:"1" 5-3:"Bit index (b3)" 2-0:"Operand (r8)" ;
192+
}}

0 commit comments

Comments
 (0)