Apply new section name style

Author: ISSOtm

CONTRIBUTING.md

@@ -130,7 +130,7 @@ Multiple registers must be handled as a memory range, and the `REG_NAME` and `De
 
 Examples:
 - 0104–0133 — Nintendo Logo
-- FF51–FF52 — HDMA1, HDMA2 (CGB Mode Only): New DMA Source (High, Low) \[write-only\]
+- FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): New DMA Source (High, Low) \[write-only\]
 
 It also follows that descriptions should not use commas outside of acting as separators for the aforementioned lists.
 

src/CGB_Registers.md

@@ -1,7 +1,7 @@
 # CGB Registers
 
 This chapter describes only Game Boy Color (GBC or CGB) registers that didn't
-fit into normal categories - most CGB registers are described in the
+fit into normal categories — most CGB registers are described in the
 chapter about Video Display (Color Palettes, VRAM Bank, VRAM DMA
 Transfers, and changed meaning of Bit 0 of LCDC Control register). Also,
 a changed bit is noted in the chapter about the Serial/Link port.
@@ -28,7 +28,7 @@ use "repaired" color palette data matching for GBA displays.
 
 ### LCD VRAM DMA Transfers
 
-#### FF51 - HDMA1 (New DMA Source, High) (W), FF52 - HDMA2 (New DMA Source, Low) (W) - CGB Mode Only
+#### FF51–FF52 — HDMA1, HDMA2 (CGB Mode only): VRAM DMA source (high, low) \[write-only\]
 
 These two registers specify the address at which the transfer will read
 data from. Normally, this should be either in ROM, SRAM or WRAM, thus
@@ -38,13 +38,13 @@ address in VRAM will cause garbage to be copied.
 
 The four lower bits of this address will be ignored and treated as 0.
 
-#### FF53 - HDMA3 (New DMA Destination, High) (W), FF54 - HDMA4 (New DMA Destination, Low) (W) - CGB Mode Only
+#### FF53–FF54 — HDMA3, HDMA4 (CGB Mode only): VRAM DMA destination (high, low) \[write-only\]
 
 These two registers specify the address within 8000-9FF0 to which the
 data will be copied. Only bits 12-4 are respected; others are ignored.
 The four lower bits of this address will be ignored and treated as 0.
 
-#### FF55 - HDMA5 (New DMA Length/Mode/Start) (W) - CGB Mode Only
+#### FF55 — HDMA5 (CGB Mode only): VRAM DMA length/mode/start
 
 These registers are used to initiate a DMA transfer from ROM or RAM to
 VRAM. The Source Start Address may be located at 0000-7FF0 or A000-DFF0,
@@ -58,7 +58,7 @@ specify the Transfer Length (divided by 10h, minus 1), that is, lengths of
 10h-800h bytes can be defined by the values 00h-7Fh. The upper bit
 indicates the Transfer Mode:
 
-##### Bit 7 = 0 - General Purpose DMA
+##### Bit 7 = 0 — General-Purpose DMA
 
 When using this transfer method,
 all data is transferred at once. The execution of the program is halted
@@ -69,7 +69,7 @@ the Display is disabled, or during VBlank, or (for rather short blocks)
 during HBlank. The execution of the program continues when the transfer
 has been completed, and FF55 then contains a value of FFh.
 
-##### Bit 7 = 1 - HBlank DMA
+##### Bit 7 = 1 — HBlank DMA
 
 The HBlank DMA transfers 10h bytes of
 data during each HBlank, that is, at LY=0-143, no data is transferred during
@@ -122,7 +122,7 @@ Speed Mode).
 The CGB has twice the VRAM of the DMG, but it is banked and either bank
 has a different purpose.
 
-#### FF4F - VBK - CGB Mode Only - VRAM Bank (R/W)
+#### FF4F — VBK (CGB Mode only): VRAM bank
 
 This register can be written to change VRAM banks. Only bit 0
 matters, all other bits are ignored.
@@ -137,7 +137,7 @@ corresponding Tile Maps.
 Reading from this register will return the number of the currently
 loaded VRAM bank in bit 0, and all other bits will be set to 1.
 
-### FF4D - KEY1 - CGB Mode Only - Prepare Speed Switch
+### FF4D — KEY1 (CGB Mode only): Prepare speed switch
 
 ```
  Bit 7: Current Speed     (0=Normal, 1=Double) (Read Only)
@@ -180,19 +180,19 @@ And the following will keep operating as usual:
 The CPU stops for 2050 cycles (= 8200 clocks) after the `stop` instruction is
 executed. During this time, the CPU is in a strange state. `DIV` does not tick, so
 *some* audio events are not processed. Additionally, VRAM/OAM/... locking is "frozen", yielding
-different results depending on the [STAT mode](<#FF41 - STAT (LCD Status) (R/W)>) it's started in:
+different results depending on the [STAT mode](<#FF41 — STAT: LCD status>) it's started in:
 
 - HBlank / VBlank (Mode 0 / Mode 1): The PPU cannot access any video memory, and produces black pixels
 - OAM scan (Mode 2): The PPU can access VRAM just fine, but not OAM, leading to rendering background, but not sprites
 - Rendering (Mode 3): The PPU can access everything correctly, and so rendering is not affected
 
 TODO: confirm whether interrupts can occur (just the joypad one?) during the pause, and consequences if so
 
-### FF56 - RP - CGB Mode Only - Infrared Communications Port
+### FF56 — RP (CGB Mode only): Infrared communications port
 
 This register allows to input and output data through the CGBs built-in
 Infrared Port. When reading data, bit 6 and 7 must be set (and obviously
-Bit 0 must be cleared - if you don't want to receive your own Game Boy's
+Bit 0 must be cleared — if you don't want to receive your own Game Boy's
 IR signal). After sending or receiving data you should reset the
 register to 00h to reduce battery power consumption again.
 
@@ -210,7 +210,7 @@ ON/OFF pulses (length 10us ON, 17.5us OFF each) instead of a permanent
 880us LED ON signal. Even though being generally CGB compatible, the GBA
 does not include an infra-red port.
 
-### FF6C - OPRI - CGB Mode Only - Object Priority Mode
+### FF6C — OPRI (CGB Mode only): Object priority mode
 
 This register serves as a flag for which object priority mode to use. While
 the DMG prioritizes objects by x-coordinate, the CGB prioritizes them by
@@ -229,7 +229,7 @@ It is not known if triggering a PSM NMI, which remaps the boot ROM, has an effec
 Bit 0: OBJ Priority Mode (0=OAM Priority, 1=Coordinate Priority) (Read/Write)
 ```
 
-### FF70 - SVBK - CGB Mode Only - WRAM Bank
+### FF70 — SVBK (CGB Mode only): WRAM bank
 
 In CGB Mode 32 KBytes internal RAM are available. This memory is divided
 into 8 banks of 4 KBytes each. Bank 0 is always available in memory at
@@ -249,28 +249,27 @@ unknown (if any). It isn't recommended to use them in your software,
 but you could, for example, use them to check if you are running on an
 emulator or on DMG hardware.
 
-### FF72 - Bits 0-7 (Read/Write), FF73 - Bits 0-7 (Read/Write)
+### FF72–FF73 — Bits 0–7 (CGB Mode only)
 
-Both of these registers are fully read/write. Their initial value is
-$00.
+Both of these registers are fully read/write.
+Their initial value is $00.
 
-### FF74 - Bits 0-7 (Read/Write) - CGB Mode Only
+### FF74 — Bits 0–7 (CGB Mode only)
 
-In CGB mode, this register is fully readable and writable. Its initial
-value is $00.
+In CGB mode, this register is fully readable and writable.
+Its initial value is $00.
 
 Otherwise, this register is read-only, and locked at value $FF.
 
-### FF75 - Bits 4-6 (Read/Write)
+### FF75 — Bits 4–6 (CGB Mode only)
 
-Only bits 4, 5 and 6 of this register are read/write enabled. Their
-initial value is 0.
+Only bits 4, 5 and 6 of this register are read/write enabled.
+Their initial value is 0.
 
-### FF76 - PCM12 - PCM amplitudes 1 & 2 (Read Only)
+### FF76 — PCM12 (CGB Mode only): PCM amplitudes 1 & 2 \[read-only\]
 
-This register is read-only. The low nibble is a copy of sound channel
-\#1's PCM amplitude, the high nibble a copy of sound channel \#2's.
+The low nibble is a copy of sound channel \#1's PCM amplitude, the high nibble a copy of sound channel \#2's.
 
-### FF77 - PCM34 - PCM amplitudes 3 & 4 (Read Only)
+### FF77 — PCM34 (CGB Mode only): PCM amplitudes 3 & 4 \[read-only\]
 
 Same, but with channels 3 and 4.

src/Interrupt_Sources.md

@@ -1,8 +1,8 @@
 # Interrupt Sources
 
-## INT 40 - VBlank Interrupt
+## INT $40 — VBlank interrupt
 
-This interrupt is requested every time the Game Boy enters VBlank ([Mode 1](<#FF41 - STAT (LCD Status) (R/W)>)).
+This interrupt is requested every time the Game Boy enters VBlank ([Mode 1](<#FF41 — STAT: LCD status>)).
 
 The VBlank interrupt occurs ca. 59.7 times a second on a handheld Game
 Boy (DMG or CGB) or Game Boy Player and ca. 61.1 times a second on a
@@ -11,10 +11,10 @@ VBlank period (LY=144). During this period video hardware is not using
 VRAM so it may be freely accessed. This period lasts approximately 1.1
 milliseconds.
 
-## INT 48 - STAT Interrupt
+## INT $48 — STAT interrupt
 
 There are various sources which can trigger this interrupt to occur as
-described in [STAT register (\$FF41)](<#FF41 - STAT (LCD Status) (R/W)>).
+described in [STAT register (\$FF41)](<#FF41 — STAT: LCD status>).
 
 The various STAT interrupt sources (modes 0-2 and LYC=LY) have their 
 state (inactive=low and active=high) logically ORed into a shared
@@ -30,7 +30,7 @@ If a STAT interrupt source logically ORs the interrupt line high while
 there will be no low-to-high transition and so no interrupt will occur. 
 This phenomenon is known as "STAT blocking" ([test ROM example](https://github.com/Gekkio/mooneye-gb/blob/2d52008228557f9e713545e702d5b7aa233d09bb/tests/acceptance/ppu/stat_irq_blocking.s#L21-L22)).
 
-As mentioned in the description of the [STAT register](<#FF41 - STAT (LCD Status) (R/W)>),
+As mentioned in the description of the [STAT register](<#FF41 — STAT: LCD status>),
 the PPU cycles through the different modes in a fixed order. So for 
 example, if interrupts are enabled for two consecutive modes such as 
 Mode 0 and Mode 1, then no interrupt will trigger for Mode 1 (since 
@@ -50,14 +50,14 @@ the handler disable sprites. This can be used if you use the window for
 a text box (at the bottom of the screen), and you want sprites to be
 hidden by the text box.
 
-## INT 50 - Timer Interrupt
+## INT $50 — Timer interrupt
 
-Every time that the timer overflows (that is, when [TIMA](<#FF05 - TIMA - Timer counter (R/W)>) exceeds $FF),
+Every time that the timer overflows (that is, when [TIMA](<#FF05 — TIMA: Timer counter>) exceeds $FF),
 an interrupt is requested by setting bit 2 in the IF register
 ($FF0F). As soon as that interrupt is enabled, the CPU will execute it by
 calling the timer interrupt vector at $0050.
 
-## INT 58 - Serial Interrupt
+## INT $58 — Serial interrupt
 
 **XXXXXX\...**
 
@@ -96,15 +96,15 @@ port and a byte to be shifted into \$FF01:
 The Game Boy does not support wake-on-LAN. Completion of an externally
 clocked serial transfer does not exit STOP mode.
 
-## INT 60 - Joypad Interrupt
+## INT $60 — Joypad interrupt
 
-The Joypad interrupt is requested when any of [`P1`](<#FF00 - P1/JOYP - Joypad (R/W)>) bits 0-3 change
+The Joypad interrupt is requested when any of [`P1`](<#FF00 — P1/JOYP: Joypad>) bits 0-3 change
 from High to Low. This happens when a button is
 pressed (provided that the action/direction buttons are enabled by
 bit 5/4, respectively), however, due to switch bounce, one or more High to Low
 transitions are usually produced when pressing a button.
 
-### Using the Joypad Interrupt
+### Using the joypad interrupt
 
 This interrupt is useful to identify button presses if we have only selected
 either action (bit 5) or direction (bit 4), but not both.

src/Interrupts.md

@@ -1,6 +1,6 @@
 # Interrupts
 
-## IME - Interrupt Master Enable Flag (Write Only)
+## IME: Interrupt master enable flag \[write only\]
 
 ```
 0 - Disable all interrupts
@@ -26,7 +26,7 @@ The effect of `ei` is delayed by one instruction. This means that `ei`
 followed immediately by `di` does not allow any interrupts between them.
 This interacts with the [`halt` bug](<#halt bug>) in an interesting way.
 
-## FFFF - IE - Interrupt Enable (R/W)
+## FFFF — IE: Interrupt enable
 
 ```
 Bit 0: VBlank   Interrupt Enable  (INT $40)  (1=Enable)
@@ -36,7 +36,7 @@ Bit 3: Serial   Interrupt Enable  (INT $58)  (1=Enable)
 Bit 4: Joypad   Interrupt Enable  (INT $60)  (1=Enable)
 ```
 
-## FF0F - IF - Interrupt Flag (R/W)
+## FF0F — IF: Interrupt flag
 
 ```
 Bit 0: VBlank   Interrupt Request (INT $40)  (1=Request)
@@ -66,7 +66,7 @@ unless/until IME and IE allow it.
 1. The IF bit corresponding to this interrupt and the IME flag are reset by the CPU.
 The former "acknowledges" the interrupt, while the latter prevents any further interrupts
 from being handled until the program re-enables them, typically by using the `reti` instruction.
-2. The corresponding interrupt handler (see the IE and IF register descriptions [above](<#FFFF - IE - Interrupt Enable (R/W)>)) is
+2. The corresponding interrupt handler (see the IE and IF register descriptions [above](<#FFFF — IE: Interrupt enable>)) is
 called by the CPU. This is a regular call, exactly like what would be performed by a `call <address>` instruction (the current PC is pushed onto the stack
 and then set to the address of the interrupt handler).
 

src/Joypad_Input.md

@@ -1,6 +1,6 @@
 # Joypad Input
 
-## FF00 - P1/JOYP - Joypad (R/W)
+## FF00 — P1/JOYP: Joypad
 
 The eight Game Boy action/direction buttons are arranged as a 2x4
 matrix. Select either action or direction buttons by writing to this

src/LCDC.md

@@ -1,6 +1,6 @@
 # LCD Control
 
-## FF40 - LCDC (LCD Control) (R/W)
+## FF40 — LCDC: LCD control
 
 **LCDC** is the main **LCD C**ontrol register. Its bits toggle what
 elements are displayed on the screen, and how.
@@ -16,7 +16,7 @@ Bit | Name                           | Usage notes
  1  | OBJ enable                     | 0=Off, 1=On
  0  | BG and Window enable/priority  | 0=Off, 1=On
 
-### LCDC.7 - LCD enable
+### LCDC.7 — LCD enable
 
 This bit controls whether the LCD is on and the PPU is active. Setting
 it to 0 turns both off, which grants immediate and full access to VRAM,
@@ -42,25 +42,25 @@ picture sticks to the screen. (TODO: research this more.)
 When re-enabling the LCD, the PPU will immediately start drawing again,
 but the screen will stay blank during the first frame.
 
-### LCDC.6 - Window tile map area
+### LCDC.6 — Window tile map area
 
 This bit controls which background map the Window uses for rendering.
 When it's reset, the \$9800 tilemap is used, otherwise it's the \$9C00
 one.
 
-### LCDC.5 - Window enable
+### LCDC.5 — Window enable
 
 This bit controls whether the window shall be displayed or not.
-This bit is overridden on DMG by [bit 0](<#LCDC.0 - BG and Window enable/priority>)
+This bit is overridden on DMG by [bit 0](<#LCDC.0 — BG and Window enable/priority>)
 if that bit is reset.
 
 Changing the value of this register mid-frame triggers a more complex behaviour:
-[see further below](<#FF4A - WY (Window Y Position) (R/W), FF4B - WX (Window X Position + 7) (R/W)>).
+[see further below](<#FF4A–FF4B — WY, WX: Window Y position, X position plus 7>).
 
 Note that on CGB models, setting this bit to 0 then back to 1 mid-frame
 may cause the second write to be ignored. (TODO: test this.)
 
-### LCDC.4 - BG and Window tile data area
+### LCDC.4 — BG and Window tile data area
 
 This bit controls which [addressing
 mode](<#VRAM Tile Data>) the BG and Window use to
@@ -69,21 +69,21 @@ pick tiles.
 Sprites aren't affected by this, and will always use \$8000 addressing
 mode.
 
-### LCDC.3 - BG tile map area
+### LCDC.3 — BG tile map area
 
-This bit works similarly to [LCDC bit 6](<#LCDC.6 - Window tile map area>):
+This bit works similarly to [LCDC bit 6](<#LCDC.6 — Window tile map area>):
 if the bit is reset, the BG uses tilemap $9800, otherwise tilemap $9C00.
 
 
-### LCDC.2 - OBJ size
+### LCDC.2 — OBJ size
 
 This bit controls the sprite size (1 tile or 2 stacked vertically).
 
 Be cautious when changing this mid-frame from 8x8 to 8x16: "remnants"
 of the sprites intended for 8x8 could "leak" into the 8x16 zone and
 cause artifacts.
 
-### LCDC.1 - OBJ enable
+### LCDC.1 — OBJ enable
 
 This bit toggles whether sprites are displayed or not.
 
@@ -93,18 +93,18 @@ displayed on top of a status bar or text box.
 (Note: toggling mid-scanline might have funky results on DMG?
 Investigation needed.)
 
-### LCDC.0 - BG and Window enable/priority
+### LCDC.0 — BG and Window enable/priority
 
 LCDC.0 has different meanings depending on Game Boy type and Mode:
 
-#### Non-CGB Mode (DMG, SGB and CGB in compatibility mode): BG and Window Display
+#### Non-CGB Mode (DMG, SGB and CGB in compatibility mode): BG and Window display
 
 When Bit 0 is cleared, both background and window become blank (white),
-and the [Window Display Bit](<#LCDC.5 - Window enable>)
+and the [Window Display Bit](<#LCDC.5 — Window enable>)
 is ignored in that case. Only Sprites may still be displayed (if enabled
 in Bit 1).
 
-#### CGB Mode: BG and Window Master Priority
+#### CGB Mode: BG and Window master priority
 
 When Bit 0 is cleared, the background and window lose their priority -
 the sprites will be always displayed on top of background and window,

src/M161.md

@@ -19,14 +19,14 @@ Since 4th output pin will be high, the signal cannot become low anymore, thus pr
 
 ## Memory
 
-### 0000-7FFF - ROM Bank $00-$07 (Read Only)
+### 0000-7FFF — ROM Bank $00-$07 \[read only\]
 
 This area contains a 32 KiB bank of ROM.
 On startup, this will contain the first 32 KiB of ROM (bank 0).
 
 ## Registers
 
-### 0000-7FFF - ROM Bank Number (Write Only)
+### 0000-7FFF — ROM Bank Number \[write only\]
 
 This 3-bit register (range $00-$07) selects the ROM bank number for the $0000-$7FFF region.
 Like other mappers, the high bits are discarded.
@@ -36,7 +36,7 @@ Only 1 bankswitch is allowed per session, once any write to this register occurs
 ## Operation Notes
 
 Because the full 32 KiB range is switched over, caution should be taken, as the entire ROM range will change.
-It may be best to have the bankswitch code placed right before $0100, so as to fall through to [the game's init sequence](<#0100-0103 - Entry Point>).
+It may be best to have the bankswitch code placed right before $0100, so as to fall through to [the game's init sequence](<#0100-0103 — Entry point>).
 
 ### References