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::: tip TERMINOLOGY
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- All references to a cycle are meant as T-cycles (4.19 MHz) and cycle
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- counts are doubled on CGB in double speed mode. When it is stated that a
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- certain action * lengthens mode 3* it means that mode 0 (hblank ) is
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+ All references to a dot are meant as dots (4.19 MHz). Dots remain the same regardless of
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+ CGB double speed.
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+ When it is stated that a certain action * lengthens mode 3* it means that mode 0 (HBlank ) is
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shortened to make up for the additional time in mode 3, as shown in the following diagram.
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:::
@@ -37,8 +37,8 @@ Each pixel in the FIFO has four properties:
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The fetcher fetches a row of 8 background or window pixels and queues
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them up to be mixed with sprite pixels. The pixel fetcher has 5 steps.
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- The first four steps take 2 cycles each and the fifth step is attempted
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- every cycle until it succeeds. The order of the steps are as follows:
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+ The first four steps take 2 dots each and the fifth step is attempted
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+ every dot until it succeeds. The order of the steps are as follows:
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- Get tile
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- Get tile data low
@@ -75,7 +75,7 @@ VRAM. However, if the PPU's access to VRAM is [blocked](<#VRAM Access>)
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then the value for the tile is read as $FF.
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CGB can access both tile index and the attributes in the same clock
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- cycle .
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+ dot .
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### Get Tile Data Low
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@@ -143,7 +143,7 @@ are cleared.
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When rendering the window the background FIFO is cleared and the fetcher
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is reset to step 1. When WX is 0 and the SCX & 7 > 0 mode 3 is shortened
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- by 1 cycle .
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+ by 1 dot .
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When the window has already started rendering there is a bug that occurs
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when WX is changed mid-scanline. When the value of WX changes after the
@@ -160,26 +160,26 @@ met then sprite fetching is [aborted](<#Sprite Fetch Abortion>).
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At this point the [ fetcher] ( < #FIFO Pixel Fetcher > ) is advanced one step
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until it's at step 5 or until the background FIFO is not empty. Advancing
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- the fetcher one step here lengthens mode 3 by 1 cycle . This process may
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+ the fetcher one step here lengthens mode 3 by 1 dot . This process may
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be [ aborted] ( < #Sprite Fetch Abortion > ) after the fetcher has advanced a
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step.
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When SCX & 7 > 0 and there is a sprite at X coordinate 0 of the current
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- scanline then mode 3 is lengthened. The amount of cycles this lengthens
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+ scanline then mode 3 is lengthened. The amount of dots this lengthens
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mode 3 by is whatever the lower 3 bits of SCX are. After this penalty is
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applied object fetching may be aborted. Note that the timing of the
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penalty is not confirmed. It may happen before or after waiting for the
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fetcher. More research needs to be done.
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After checking for sprites at X coordinate 0 the fetcher is advanced two
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- steps. The first advancement lengthens mode 3 by 1 cycle and the second
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- advancement lengthens mode 3 by 3 cycles . After each fetcher advancement
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+ steps. The first advancement lengthens mode 3 by 1 dot and the second
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+ advancement lengthens mode 3 by 3 dots . After each fetcher advancement
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there is a chance for a sprite fetch abortion to occur.
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The lower address for the row of pixels of the target object tile is now
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- retrieved and lengthens mode 3 by 1 cycle . Once the address is retrieved
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+ retrieved and lengthens mode 3 by 1 dot . Once the address is retrieved
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this is the last chance for sprite fetch abortion to occur. Exiting
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- object fetch lengthens mode 3 by 1 cycle . The upper address for the
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+ object fetch lengthens mode 3 by 1 dot . The upper address for the
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target object tile is now retrieved and does not shorten mode 3.
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At this point [ VRAM Access] ( < #VRAM Access > ) is checked for the lower and
@@ -195,7 +195,7 @@ is replaced with the target object's properties.
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Now it's time to [ render a pixel] ( < #Pixel Rendering > ) ! The same process
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described in Sprite Fetch Abortion is performed: a pixel is rendered and
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the fetcher is advanced one step. This advancement lengthens mode 3 by 1
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- cycle if the X coordinate of the current scanline is not 160. If the X
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+ dot if the X coordinate of the current scanline is not 160. If the X
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coordinate is 160 the PPU stops processing sprites (because they won't be
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visible).
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@@ -245,12 +245,12 @@ blocked and a black pixel pushed to the LCD when rendering pixels:
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- First HBlank of the frame
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- When searching OAM and index 37 is reached
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- After switching from mode 2 (oam search) to mode 3 (pixel transfer)
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- - When entering HBlank (mode 0) and not in double speed mode, blocked 2 cycles later no matter what
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+ - When entering HBlank (mode 0) and not in double speed mode, blocked 2 dots later no matter what
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At various times during PPU operation read access to the CGB palette is
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restored and pixels are pushed to the LCD normally when rendering pixels:
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- At the end of mode 2 (oam search)
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- - For only 2 cycles when entering HBlank (mode 0) and in double speed mode
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+ - For only 2 dots when entering HBlank (mode 0) and in double speed mode
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::: tip Note
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@@ -263,9 +263,9 @@ PPU's access to CGB palettes is always restored upon leaving STOP mode.
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Sprite fetching may be aborted if LCDC.1 is disabled while the PPU is
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fetching an object from OAM. This abortion lengthens mode 3 by the amount
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- of cycles the previous instruction took plus the residual cycles left for
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+ of dots the previous instruction took plus the residual dots left for
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the PPU to process. When OAM fetching is aborted a pixel is [ rendered] ( < #Pixel Rendering > ) ,
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the [ fetcher] ( < #FIFO Pixel Fetcher > ) is advanced one step. This advancement
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- lengthens mode 3 by 1 cycle if the current pixel is not 160. If the
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+ lengthens mode 3 by 1 dot if the current pixel is not 160. If the
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current pixel is 160 the PPU stops processing sprites because they won't
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be visible.
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