Make hexadecimal numbers follow the style guide (#473)

* Make hexadecimal numbers follow the style guide
* Add link to joypad register

---------

Co-authored-by: Antonio Vivace <[email protected]>
Co-authored-by: Eldred Habert <[email protected]>

Author: 3 people

src/CGB_Registers.md

@@ -9,17 +9,17 @@ a changed bit is noted in the chapter about the Serial/Link port.
 ## Unlocking CGB functions
 
 When using any CGB registers (including those in the Video/Link
-chapters), you must first unlock CGB features by changing byte 0143h in
-the cartridge header. Typically, use a value of 80h for games which
-support both CGB and monochrome Game Boy systems, and C0h for games which work
+chapters), you must first unlock CGB features by changing byte 0143 in
+the cartridge header. Typically, use a value of $80 for games which
+support both CGB and monochrome Game Boy systems, and $C0 for games which work
 on CGBs only. Otherwise, the CGB will operate in monochrome "Non CGB"
 compatibility mode.
 
 ## Detecting CGB (and GBA) functions
 
 CGB hardware can be detected by examining the CPU accumulator (A-register)
-directly after startup. A value of 11h indicates CGB (or GBA) hardware,
-if so, CGB functions can be used (if unlocked, see above). When A=11h,
+directly after startup. A value of $11 indicates CGB (or GBA) hardware,
+if so, CGB functions can be used (if unlocked, see above). When A=$11,
 you may also examine Bit 0 of the CPUs B-Register to separate between
 CGB (bit cleared) and GBA (bit set), by that detection it is possible to
 use "repaired" color palette data matching for GBA displays.
@@ -54,8 +54,8 @@ bits of the address are ignored (treated as zero), the upper 3 bits are
 ignored either (destination is always in VRAM).
 
 Writing to this register starts the transfer, the lower 7 bits of which
-specify the Transfer Length (divided by 10h, minus 1), that is, lengths of
-10h-800h bytes can be defined by the values 00h-7Fh. The upper bit
+specify the Transfer Length (divided by $10, minus 1), that is, lengths of
+$10-$800 bytes can be defined by the values $00-$7F. The upper bit
 indicates the Transfer Mode:
 
 ##### Bit 7 = 0 — General-Purpose DMA
@@ -67,11 +67,11 @@ blindly attempts to copy the data, even if the LCD controller is
 currently accessing VRAM. So General Purpose DMA should be used only if
 the Display is disabled, or during VBlank, or (for rather short blocks)
 during HBlank. The execution of the program continues when the transfer
-has been completed, and FF55 then contains a value of FFh.
+has been completed, and FF55 then contains a value of $FF.
 
 ##### Bit 7 = 1 — HBlank DMA
 
-The HBlank DMA transfers 10h bytes of
+The HBlank DMA transfers $10 bytes of
 data during each HBlank, that is, at LY=0-143, no data is transferred during
 VBlank (LY=144-153), but the transfer will then continue at LY=00. The
 execution of the program is halted during the separate transfers, but
@@ -81,8 +81,8 @@ block. Note that the program should not change the Destination VRAM bank
 bankable memory) until the transfer has completed! (The transfer should
 be paused as described below while the banks are switched)
 
-Reading from Register FF55 returns the remaining length (divided by 10h,
-minus 1), a value of 0FFh indicates that the transfer has completed. It
+Reading from Register FF55 returns the remaining length (divided by $10,
+minus 1), a value of $FF indicates that the transfer has completed. It
 is also possible to terminate an active HBlank transfer by writing zero
 to Bit 7 of FF55. In that case reading from FF55 will return how many
 \$10 "blocks" remained (minus 1) in the lower 7 bits, but Bit 7 will
@@ -194,7 +194,7 @@ This register allows to input and output data through the CGBs built-in
 Infrared Port. When reading data, bit 6 and 7 must be set (and obviously
 Bit 0 must be cleared — if you don't want to receive your own Game Boy's
 IR signal). After sending or receiving data you should reset the
-register to 00h to reduce battery power consumption again.
+register to $00 to reduce battery power consumption again.
 
 ```
  Bit 0:   Write Data   (0=LED Off, 1=LED On)             (Read/Write)
@@ -239,7 +239,7 @@ C000-CFFF, Bank 1-7 can be selected into the address space at D000-DFFF.
  Bit 0-2  Select WRAM Bank (Read/Write)
 ```
 
-Writing a value of 01h-07h will select Bank 1-7, writing a value of 00h
+Writing a value of $01-$07 will select Bank 1-7, writing a value of $00
 will select Bank 1 too.
 
 ## Undocumented registers

src/Gameboy_Camera.md

@@ -38,19 +38,19 @@ This area may contain any ROM bank (0 included). The initial mapped bank is 01.
 
 ### A000-BFFF - CAM Registers (Read/Write)
 
-Depending on the current RAM Bank Number, this memory space is used to access the cartridge RAM or the CAM registers. RAM can only be read if the capture unit is not working, it returns 00h otherwise.
+Depending on the current RAM Bank Number, this memory space is used to access the cartridge RAM or the CAM registers. RAM can only be read if the capture unit is not working, it returns $00 otherwise.
 
 ### 0000-1FFF - RAM Enable (Write Only)
 
-A value of 0Ah will enable writing to RAM, 00h will disable it. Reading from RAM or registers is always enabled. Writing to registers is always enabled. Disabled on reset.
+A value of $0A will enable writing to RAM, $00 will disable it. Reading from RAM or registers is always enabled. Writing to registers is always enabled. Disabled on reset.
 
 ### 2000-3FFF - ROM Bank Number (Write Only)
 
-Writing a value of 00-3Fh selects the corresponding ROM Bank for area 4000-7FFF.
+Writing a value of $00-$3F selects the corresponding ROM Bank for area 4000-7FFF.
 
 ### 4000-5FFF - RAM Bank Number/CAM Registers Select (Write Only)
 
-Writing a value in range for 00h-0Fh maps the corresponding external RAM Bank to memory at A000-BFFF. Writing any value with bit 4 set to '1' will select CAM registers. Usually bank 10h is used to select the registers. All registers are mirrored every 80h bytes. RAM bank 0 selected on reset.
+Writing a value in range for $00-$0F maps the corresponding external RAM Bank to memory at A000-BFFF. Writing any value with bit 4 set to '1' will select CAM registers. Usually bank $10 is used to select the registers. All registers are mirrored every $80 bytes. RAM bank 0 selected on reset.
 
 ::: tip NOTE
 
@@ -60,20 +60,20 @@ Unlike most games, the GB Camera RAM can only be written when PHI pin = '1'. It'
 
 ## I/O Registers
 
-The Game Boy Camera I/O registers are mapped to all banks with bit 4 set to '1'. The GB Camera ROM usually changes to bank 16 (10h) to use the registers.
+The Game Boy Camera I/O registers are mapped to all banks with bit 4 set to '1'. The GB Camera ROM usually changes to bank 16 ($10) to use the registers.
 
 There are 3 groups of registers:
 - The first group is composed by the trigger register A000. This register starts the capture process and returns the current status (working/capture finished).
 - The second group is composed by registers A001-A005, used to configure most parameters of the M64282FP sensor.
 - The third group is composed by 48 registers that form a 4×4 matrix. Each element of the matrix is formed by 3 bytes. This matrix is used by the controller for contrast and dithering.
 
-All registers are write-only, except the register A000. The others return 00h when read. The initial values of all registers on reset is 00h.
+All registers are write-only, except the register A000. The others return $00 when read. The initial values of all registers on reset is $00.
 
 ### Register A000
 
 The lower 3 bits of this register can be read and write. The other bits return '0'. Writing any value with bit 0 set to '1' will start the capturing process. Any write with bit 0 set to '0' is a normal write and won't trigger the capture. The value of bits 1 and 2 affects the value written to registers 4, 5 and 6 of the M64282FP, which are used in 1-D filtering mode (effects described in following chapters).
 Bit 0 of this register is also used to verify if the capturing process is finished. It returns '1' when the hardware is working and '0' if the capturing process is over.
-When the capture process is active all RAM banks will return 00h when read (and writes are ignored), but the register A000 can still be read to know when the transfer is finished.
+When the capture process is active all RAM banks will return $00 when read (and writes are ignored), but the register A000 can still be read to know when the transfer is finished.
 The capturing process can be stopped by writing a '0' to bit 0. When a '1' is written again it will continue the previous capture process with the old capture parameters, even if the registers are changed in between. If the process is stopped RAM can be read again.
 
 ### Register A001

src/MBC1.md

@@ -41,7 +41,7 @@ External RAM is often battery-backed, allowing for the storage of game data whil
 
 ## Registers
 
-All of the MBC1 registers default to 00h on power-up, which for the "ROM Bank Number" register is _treated as_ 01h.
+All of the MBC1 registers default to $00 on power-up, which for the "ROM Bank Number" register is _treated as_ $01.
 
 ### 0000–1FFF — RAM Enable (Write Only)
 
@@ -82,7 +82,7 @@ effective bank number:
 
 [^MBC1M_banking]: MBC1M has a different formula, see below
 
-These additional two bits are ignored for the bank 00→01 translation. This causes a problem — attempting to access banks 20h, 40h, and 60h only set bits in the upper 2-bit register, with the lower 5-bit register set to 00. As a result, any
+These additional two bits are ignored for the bank 00→01 translation. This causes a problem — attempting to access banks $20, $40, and $60 only set bits in the upper 2-bit register, with the lower 5-bit register set to 00. As a result, any
 attempt to address these ROM Banks will select Bank $21, $41 and $61
 instead. The only way to access banks $20, $40 or $60 at all is to enter mode 1,
 which remaps the 0000–3FFF range. This has its own problems for game

src/MBC3.md

@@ -15,7 +15,7 @@ Contains the first 16 KiB of the ROM.
 
 ### 4000-7FFF - ROM Bank 01-7F (Read Only)
 
-Same as for MBC1, except that accessing banks 20h, 40h, and 60h is
+Same as for MBC1, except that accessing banks $20, $40, and $60 is
 supported now.
 
 ### A000-BFFF - RAM Bank 00-03, if any (Read/Write)
@@ -34,42 +34,42 @@ single RTC Register.
 
 ### 0000-1FFF - RAM and Timer Enable (Write Only)
 
-Mostly the same as for MBC1, a value of 0Ah will enable reading and
-writing to external RAM - and to the RTC Registers! A value of 00h will
+Mostly the same as for MBC1, a value of $0A will enable reading and
+writing to external RAM - and to the RTC Registers! A value of $00 will
 disable either.
 
 ### 2000-3FFF - ROM Bank Number (Write Only)
 
 Same as for MBC1, except that the whole 7 bits of the ROM Bank Number
 are written directly to this address. As for the MBC1, writing a value
-of 00h will select Bank 01h instead. All other values 01-7Fh select the
+of $00 will select Bank $01 instead. All other values $01-$7F select the
 corresponding ROM Banks.
 
 ### 4000-5FFF - RAM Bank Number - or - RTC Register Select (Write Only)
 
-As for the MBC1s RAM Banking Mode, writing a value in range for 00h-03h
+As for the MBC1s RAM Banking Mode, writing a value in range for $00-$03
 maps the corresponding external RAM Bank (if any) into memory at
-A000-BFFF. When writing a value of 08h-0Ch, this will map the
+A000-BFFF. When writing a value of $08-$0C, this will map the
 corresponding RTC register into memory at A000-BFFF. That register could
 then be read/written by accessing any address in that area, typically
 that is done by using address A000.
 
 ### 6000-7FFF - Latch Clock Data (Write Only)
 
-When writing 00h, and then 01h to this register, the current time
+When writing $00, and then $01 to this register, the current time
 becomes latched into the RTC registers. The latched data will not change
-until it becomes latched again, by repeating the write 00h-\>01h
+until it becomes latched again, by repeating the write $00-\>$01
 procedure. This provides a way to read the RTC registers while the
 clock keeps ticking.
 
 ### The Clock Counter Registers
 
 ```
-08h  RTC S   Seconds   0-59 (0-3Bh)
-09h  RTC M   Minutes   0-59 (0-3Bh)
-0Ah  RTC H   Hours     0-23 (0-17h)
-0Bh  RTC DL  Lower 8 bits of Day Counter (0-FFh)
-0Ch  RTC DH  Upper 1 bit of Day Counter, Carry Bit, Halt Flag
+$08  RTC S   Seconds   0-59 ($00-$3B)
+$09  RTC M   Minutes   0-59 ($00-$3B)
+$0A  RTC H   Hours     0-23 ($00-$17)
+$0B  RTC DL  Lower 8 bits of Day Counter ($00-$FF)
+$0C  RTC DH  Upper 1 bit of Day Counter, Carry Bit, Halt Flag
       Bit 0  Most significant bit of Day Counter (Bit 8)
       Bit 6  Halt (0=Active, 1=Stop Timer)
       Bit 7  Day Counter Carry Bit (1=Counter Overflow)
@@ -81,7 +81,7 @@ Registers.
 ### The Day Counter
 
 The total 9 bits of the Day Counter allow counting days in range from
-0-511 (0-1FFh). The Day Counter Carry Bit becomes set when this value
+0-511 ($000-$1FF). The Day Counter Carry Bit becomes set when this value
 overflows. In that case the Carry Bit remains set until the program does
 reset it. Note that you can store an offset to the Day Counter in
 battery RAM. For example, every time you read a non-zero Day Counter,

src/MBC6.md

@@ -41,8 +41,8 @@ Bank A.
 
 ### 0000-03FF — RAM Enable (Write Only)
 
-Mostly the same as for MBC1, a value of 0Ah will enable reading and
-writing to external RAM. A value of 00h will disable it.
+Mostly the same as for MBC1, a value of $0A will enable reading and
+writing to external RAM. A value of $00 will disable it.
 
 ### 0400-07FF — RAM Bank A Number (Write Only)
 

src/MBC7.md

@@ -23,20 +23,20 @@ Same as for MBC5. (Bank 0 mapping needs confirmation)
 ### A000-AFFF - RAM Registers (Read/Write)
 
 Must be enabled via 0000 and 4000 region writes (see respective
-sections), otherwise reads read FFh and writes do nothing. Registers are
+sections), otherwise reads read $FF and writes do nothing. Registers are
 addressed through bits 4-7 of the address. Bits 0-3 and 8-11 are
 ignored.
 
 Accelerometer data must be latched before reading. Data is 16-bit and
 centered at the value 81D0. Earth\'s gravity affects the value by
-roughly 70h, with larger acceleration providing a larger range. Maximum
+roughly $70, with larger acceleration providing a larger range. Maximum
 range is unknown.
 
 ### Ax0x/Ax1x - Latch Accelerometer (Write Only)
 
-Write 55h to Ax0x to erase the latched data (reset back to 8000) then
-AAh to Ax1x to latch the accelerometer and update the addressable
-registers. Reads return FFh. Other writes do not appear to do anything
+Write $55 to Ax0x to erase the latched data (reset back to 8000) then
+$AA to Ax1x to latch the accelerometer and update the addressable
+registers. Reads return $FF. Other writes do not appear to do anything
 (Partially unconfirmed). Note that you cannot re-latch the accelerometer
 value without first erasing it; attempts to do so yield no change.
 
@@ -54,7 +54,7 @@ high byte. Reads 8000 before first latching.
 
 ### Ax6x/Ax7x - Unknown
 
-Ax6x always reads 00h and Ax7x always reads FFh. Possibly reserved for Z
+Ax6x always reads $00 and Ax7x always reads $FF. Possibly reserved for Z
 axis, which does not exist on this accelerometer.
 
 ### Ax8x - EEPROM (Read/Write)
@@ -74,11 +74,11 @@ manually clocking CLK. All commands must be preceded by a 1 bit, and
 existing games precede the 1 bit with a 0 bit (though this is not
 necessary):
 
--   Write 00h (lower CS)
--   Write 80h (raise CS)
--   Write C0h (shift in 0 bit)
--   Write 82h (lower CS, raise DI)
--   Write C2h (shift in 1 bit)
+-   Write $00 (lower CS)
+-   Write $80 (raise CS)
+-   Write $C0 (shift in 0 bit)
+-   Write $82 (lower CS, raise DI)
+-   Write $C2 (shift in 1 bit)
 -   Write command
 
 The following commands exist, each 10 bits (excluding data shifted in or
@@ -108,16 +108,16 @@ Datasheet:
 
 ### Ax9x-AxFx - Unused
 
-Reads out FFh.
+Reads out $FF.
 
 ### B000-BFFF - Unknown
 
-Only seems to read out FFh.
+Only seems to read out $FF.
 
 ### 0000-1FFF - RAM Enable 1 (Write Only)
 
-Mostly the same as for MBC1, a value of 0Ah will enable reading and
-writing to RAM registers. A value of 00h will disable it. Please note
+Mostly the same as for MBC1, a value of $0A will enable reading and
+writing to RAM registers. A value of $00 will disable it. Please note
 that the RAM must second be enabled in the second RAM enable section as
 well (4000-5FFF)
 
@@ -127,7 +127,7 @@ The ROM bank number goes here.
 
 ### 4000-5FFF - RAM Enable 2 (Write Only)
 
-Writing 40h to this region enables access to the RAM registers. Writing
+Writing $40 to this region enables access to the RAM registers. Writing
 any other value appears to disable access to RAM, but this is not fully
 tested. Please note that the RAM must first be enabled in the first RAM
 enable section as well (0000-1FFF)

src/MMM01.md

@@ -160,7 +160,7 @@ Bits: X 6 5 4 3 2 1 0
 
 #### Bits 0-3: RAM Enable
 
-As per MBC1, writing $Ah to the lower 4 bits enables the external RAM, and any other value disables it.
+As per MBC1, writing $A to the lower 4 bits enables the external RAM, and any other value disables it.
 The external RAM is automatically disabled when the Game Boy is powered off or the cartridge is removed.
 
 #### Bits 4-5: RAM Bank Mask

src/Reducing_Power_Consumption.md

@@ -89,8 +89,8 @@ buttons you want to terminate the STOP on).
 ## Disabling the Sound Controller
 
 If your program doesn't use sound at all (or during some periods) then
-write 00h to register FF26 to save 16% or more on GB power consumption.
-Sound can be turned back on by writing 80h to the same register, all
+write $00 to register FF26 to save 16% or more on GB power consumption.
+Sound can be turned back on by writing $80 to the same register, all
 sound registers must be then re-initialized. When the Game Boy is turned
 on, sound is enabled by default, and must be turned off manually when
 not used.

src/SGB_Color_Palettes.md

@@ -53,7 +53,7 @@ relationship between Game Boy colors 0-3 and SNES colors 0-3.
 ### Using Game Boy BGP/OBP Registers
 
 A direct translation of GB color 0-3 into SNES color 0-3 may be produced
-by setting BGP/OBPx registers to a value of 0E4h each. However, in case
+by setting BGP/OBPx registers to a value of $0E4 each. However, in case
 that your program uses black background for example, then you may
 internally assign background as "White" at the Game Boy side by BGP/OBP
 registers (which is then interpreted as SNES color 0, which is shared

src/SGB_Command_Attribute.md

@@ -8,7 +8,7 @@ more rectangular screen regions.
 ```
  Byte  Content
  0     Command*8+Length (length=1..7)
- 1     Number of Data Sets (01h..12h)
+ 1     Number of Data Sets ($01..$12)
  2-7   Data Set #1
          Byte 0 - Control Code (0-7)
            Bit 0 - Change Colors inside of surrounded area     (1=Yes)
@@ -43,7 +43,7 @@ character lines.
 ```
  Byte  Content
  0     Command*8+Length (length=1..7)
- 1     Number of Data Sets (01h..6Eh) (one byte each)
+ 1     Number of Data Sets ($01..$6E) (one byte each)
  2     Data Set #1
          Bit 0-4 - Line Number    (X- or Y-coordinate, depending on bit 7)
          Bit 5-6 - Palette Number (0-3)
@@ -135,7 +135,7 @@ Used to transfer attributes from Attribute File (ATF) to Game Boy window.
 ```
  Byte  Content
  0     Command*8+Length (fixed length=1)
- 1     Attribute File Number (00-2Ch), Bit 6=Cancel Mask
+ 1     Attribute File Number ($00-$2C), Bit 6=Cancel Mask
  2-F   Not used (zero)
 ```