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jsmattsonjrgregkh
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x86/cpufeatures: Define X86_FEATURE_AMD_IBPB_RET
commit ff89862 upstream. AMD's initial implementation of IBPB did not clear the return address predictor. Beginning with Zen4, AMD's IBPB *does* clear the return address predictor. This behavior is enumerated by CPUID.80000008H:EBX.IBPB_RET[30]. Define X86_FEATURE_AMD_IBPB_RET for use in KVM_GET_SUPPORTED_CPUID, when determining cross-vendor capabilities. Suggested-by: Venkatesh Srinivas <[email protected]> Signed-off-by: Jim Mattson <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Tom Lendacky <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Cc: <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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arch/x86/include/asm/cpufeatures.h

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@@ -216,7 +216,7 @@
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#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 7*32+23) /* "" Disable Speculative Store Bypass. */
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#define X86_FEATURE_LS_CFG_SSBD ( 7*32+24) /* "" AMD SSBD implementation via LS_CFG MSR */
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#define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */
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#define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */
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#define X86_FEATURE_IBPB ( 7*32+26) /* "ibpb" Indirect Branch Prediction Barrier without a guaranteed RSB flush */
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#define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */
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#define X86_FEATURE_ZEN ( 7*32+28) /* "" Generic flag for all Zen and newer */
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#define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */
@@ -347,6 +347,7 @@
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#define X86_FEATURE_CPPC (13*32+27) /* Collaborative Processor Performance Control */
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#define X86_FEATURE_AMD_PSFD (13*32+28) /* "" Predictive Store Forwarding Disable */
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#define X86_FEATURE_BTC_NO (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
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#define X86_FEATURE_AMD_IBPB_RET (13*32+30) /* "" IBPB clears return address predictor */
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#define X86_FEATURE_BRS (13*32+31) /* Branch Sampling available */
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/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

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