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soc: silabs bgm24 ble module
Add support for BGM24 BLE modules based on EFR32BG MCU core. Based on Gecko SDK 4.4.2 Signed-off-by: Jonny Gellhaar <[email protected]>
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11 files changed

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‎drivers/bluetooth/hci/slz_hci.c

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@@ -36,7 +36,7 @@ static struct k_thread slz_ll_thread;
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void rail_isr_installer(void)
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{
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#ifdef CONFIG_SOC_SERIES_EFR32MG24
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#if defined(CONFIG_SOC_SERIES_EFR32MG24) || defined(CONFIG_SOC_SERIES_BGM24)
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IRQ_CONNECT(SYNTH_IRQn, 0, SYNTH_IRQHandler, NULL, 0);
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#else
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IRQ_CONNECT(RDMAILBOX_IRQn, 0, RDMAILBOX_IRQHandler, NULL, 0);

‎drivers/gpio/gpio_gecko.c

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@@ -29,6 +29,7 @@
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#if defined(CONFIG_SOC_SERIES_EFR32BG22) || \
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defined(CONFIG_SOC_SERIES_EFR32BG27) || \
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defined(CONFIG_SOC_SERIES_EFR32MG21) || \
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defined(CONFIG_SOC_SERIES_BGM24) || \
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defined(CONFIG_SOC_SERIES_EFR32MG24)
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#define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_PORT_TypeDef)
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#else

‎dts/arm/silabs/bgm24-pinctrl.dtsi

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/*
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* Copyright (c) 2022 Silicon Labs
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <dt-bindings/pinctrl/gecko-pinctrl.h>
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&pinctrl {
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/* configuration for uart0 device, default state */
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usart0_default: usart0_default {
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group1 {
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/* configure PA.6 as UART_RX and PA.5 as UART_TX */
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psels = <GECKO_PSEL(UART_TX, A, 5)>,
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<GECKO_PSEL(UART_RX, A, 6)>,
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<GECKO_LOC(UART, 0)>;
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};
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};
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i2c0_default: i2c0_default {
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group1 {
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psels = <GECKO_PSEL(I2C_SDA, C, 5)>,
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<GECKO_PSEL(I2C_SCL, C, 4)>,
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<GECKO_LOC(I2C_SDA, 5)>,
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<GECKO_LOC(I2C_SCL, 5)>;
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};
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};
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};

‎dts/arm/silabs/bgm24.dtsi

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/*
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* Copyright (c) 2020 TriaGnoSys GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <arm/silabs/gpio_gecko.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/pinctrl/gecko-pinctrl.h>
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#include <dt-bindings/adc/adc.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &msc;
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zephyr,entropy = &se;
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};
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clocks {
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clk_hfxo: clk-hfxo {
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#clock-cells = <0>;
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compatible = "silabs,hfxo";
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clock-frequency = <DT_FREQ_M(39)>;
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ctune = <140>;
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precision = <50>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
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};
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power-states {
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/*
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* EM1 is a basic "CPU WFI idle", all high-freq clocks remain
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* enabled.
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*/
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pstate_em1: em1 {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <4>;
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/* HFXO remains active */
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exit-latency-us = <2>;
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};
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/*
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* EM2 is a deepsleep with HF clocks disabled by HW, voltages
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* scaled down, etc.
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*/
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pstate_em2: em2 {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <260>;
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exit-latency-us = <250>;
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};
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/*
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* EM3 seems to be exactly the same as EM2 except that
68+
* LFXO & LFRCO should be disabled, so you must use ULFRCO
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* as BURTC clock for the system to not lose track of time and
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* wake up.
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*/
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pstate_em3: em3 {
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compatible = "zephyr,power-state";
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power-state-name = "standby";
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min-residency-us = <20000>;
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exit-latency-us = <2000>;
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};
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};
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};
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sram0: memory@20000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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};
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soc {
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msc: flash-controller@50030000 {
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compatible = "silabs,gecko-flash-controller";
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reg = <0x50030000 0x3148>;
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interrupts = <50 0>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <4>;
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erase-block-size = <8192>;
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};
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};
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usart0: usart@5005c000 {
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compatible = "silabs,gecko-usart";
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reg = <0x5005C000 0x306c>;
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interrupts = <9 0>, <10 0>;
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interrupt-names = "rx", "tx";
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peripheral-id = <0>;
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status = "disabled";
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};
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burtc0: burtc@50064000 {
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compatible = "silabs,gecko-burtc";
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reg = <0x50064000 0x3034>;
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interrupts = <17 0>;
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status = "disabled";
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};
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se: semailbox@5c021000 {
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compatible = "silabs,gecko-semailbox";
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reg = <0x5c021000 0x1000>;
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status = "disabled";
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interrupts = <64 3>, <65 3>, <66 3>;
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interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
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};
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i2c0: i2c@5b000000 {
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compatible = "silabs,gecko-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x5b000000 0x3044>;
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interrupts = <27 0>;
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status = "disabled";
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};
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stimer0: stimer@500a8000 {
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compatible = "silabs,gecko-stimer";
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reg = <0x500a8000 0x3054>;
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interrupts = <67 0>;
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clock-frequency = <32768>;
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prescaler = <1>;
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status = "disabled";
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};
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gpio: gpio@5003c000 {
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compatible = "silabs,gecko-gpio";
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reg = <0x5003c000 0x4000>;
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interrupts = <26 2>, <25 2>;
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interrupt-names = "GPIO_EVEN", "GPIO_ODD";
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@5003c030 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c030 0x30>;
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peripheral-id = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiob: gpio@5003c060 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c060 0x30>;
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peripheral-id = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpioc: gpio@5003c090 {
174+
compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c090 0x30>;
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peripheral-id = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpiod: gpio@5003c0C0 {
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compatible = "silabs,gecko-gpio-port";
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reg = <0x5003c0C0 0x30>;
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peripheral-id = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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};
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wdog0: wdog@5b004000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x5b004000 0x2C>;
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peripheral-id = <0>;
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interrupts = <42 0>;
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status = "disabled";
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};
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wdog1: wdog@5b008000 {
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compatible = "silabs,gecko-wdog";
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reg = <0x5b008000 0x2C>;
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peripheral-id = <1>;
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interrupts = <43 0>;
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status = "disabled";
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};
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adc0: adc@59004000 {
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compatible = "silabs,gecko-iadc";
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reg = <0x59004000 0x4000>;
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interrupts = <49 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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bt_hci_silabs: bt_hci_silabs {
219+
compatible = "silabs,bt-hci";
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status = "disabled";
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};
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};
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/ {
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pinctrl: pin-controller {
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/* Pin controller is a "virtual" device since SiLabs SoCs do pin
227+
* control in a distributed way (GPIO registers and PSEL
228+
* registers on each peripheral).
229+
*/
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compatible = "silabs,gecko-pinctrl";
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};
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hwinfo: hwinfo {
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compatible = "silabs,gecko-hwinfo";
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status = "disabled";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};

‎dts/arm/silabs/bgm240sa22vna.dtsi

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/*
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* Copyright (c) 2023 Fr. Sauter AG
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* Copyright (c) 2024 Jonny Gellhaar
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/bgm24.dtsi>
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/ {
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sram0: memory@20000000 {
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reg = <0x20000000 DT_SIZE_K(256)>;
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};
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soc {
17+
compatible = "silabs,bgm240sa22vna",
18+
"silabs,bgm24", "silabs,efr32",
19+
"simple-bus";
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flash-controller@50030000 {
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flash0: flash@0 {
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reg = <0 DT_SIZE_K(1536)>;
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};
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};
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};
27+
};

‎soc/silabs/silabs_s2/bgm24/Kconfig

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# Silicon Labs BGM24 (Mighty Gecko) BLE module line
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# Copyright (c) 2020 TriaGnoSys GmbH
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# Copyright (c) 2024 Jonny Gellhaar
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_BGM24
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select ARM
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select CPU_CORTEX_M33
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select CPU_CORTEX_M_HAS_DWT
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select SOC_GECKO_HAS_RADIO
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select HAS_SILABS_GECKO
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select HAS_SWO
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select SOC_GECKO_CMU
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select SOC_GECKO_EMU
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select SOC_GECKO_GPIO
22+
select SOC_GECKO_DEV_INIT
23+
select SOC_GECKO_SE
24+
select HAS_PM
25+
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config SOC_GECKO_SDID
27+
default 215 if SOC_SERIES_BGM24

‎soc/silabs/silabs_s2/bgm24/Kconfig.defconfig

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# Silicon Labs BGM24 (Mighty Gecko) BLE module configuration options
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# Copyright (c) 2021 Sateesh Kotapati
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# Copyright (c) 2024 Jonny Gellhaar
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# SPDX-License-Identifier: Apache-2.0
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7+
if SOC_SERIES_BGM24
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9+
config CMU_NEED_LFXO
10+
default n
11+
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config NUM_IRQS
13+
# must be >= the highest interrupt number used
14+
default 75
15+
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config PM
17+
default n
18+
select COUNTER
19+
select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT
20+
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choice PM_POLICY
22+
default PM_POLICY_DEFAULT
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depends on PM
24+
endchoice
25+
26+
endif # SOC_SERIES_BGM24

‎soc/silabs/silabs_s2/bgm24/Kconfig.soc

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# Silicon Labs BGM24 (Mighty Gecko) BLE module line
2+
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# Copyright (c) 2020 TriaGnoSys GmbH
4+
# Copyright (c) 2024 Jonny Gellhaar
5+
# SPDX-License-Identifier: Apache-2.0
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7+
config SOC_SERIES_BGM24
8+
bool
9+
select SOC_FAMILY_SILABS_S2
10+
help
11+
BGM24 Series MCU
12+
13+
config SOC_PART_NUMBER_BGM240SA22VNA
14+
bool
15+
select SOC_SERIES_BGM24
16+
17+
config SOC_SERIES
18+
default "bgm24" if SOC_SERIES_BGM24
19+
20+
config SOC
21+
default "bgm240sa22vna" if SOC_PART_NUMBER_BGM240SA22VNA
22+
23+
config SOC_PART_NUMBER
24+
default "BGM240SA22VNA" if SOC_PART_NUMBER_BGM240SA22VNA

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