Branch for checking of clock sources

It blinks led #3, #4 by using of 100 MHz and 156.25 MHz generators.

Author: Pavel Kurochkin

README.md

@@ -1,22 +1,27 @@
-# c10gx: Serial Flash Loader
+# c10gx: led blinker 
 
-This small project is intended for writing of working firmware to configuration
-flash EPCQ256L, which is connected to the Cyclone 10GX chip.
+This project is intended for fast checking of on-board clock generators,
+connected to Cyclone 10 GX chip.  It blinks leds with 1Hz frequency. Each led
+is fed by one clock generator.
 
-## How to use
+## How it works
+
+There are two generators to be checked:
+
+  * BQ3, [DSC6102CI2A-100.0000, 100 MHz](http://ww1.microchip.com/downloads/en/DeviceDoc/20005624B.pdf). Single-ended connection 
+  * BQ2, [ASEMPLV-156.250MHZ-LR-T, 156.25 MHz](https://abracon.com/Oscillators/ASEMP.pdf). Differential connection
 
-Perform following steps to write your working bitstream (SOF) to EPCQ256L:
+Clock 100 MHz is divided by 100.000.000 and blinks led #3.
+
+Clock 156.25 MHz is divided by 156.250.000 and blinks led #3.
+
+## How to use
 
-  1. create .jic file, see [1], ch.1.5.1. At this step you should specify
-    working firmware which should be loaded from EPCQ256L
-  2. build this firmware in Quartus Prime
-  3. connect JTAG to the board
-  4. program this (sfl) firmware to FPGA. Leds 3-8 should start blinking. 
-  5. open .jic file with Quartus Prime Programmer and check
-     'Program/Configure'. Start programming. Be patient, it takes time :)
-  6. power off the board, disconnect JTAG and power on again. FPGA should run
-     with working bitstream specified in 1st step
+  1. Build led blinker firmware: open c10gx.qpf and run Full Compilation in
+     Quartus Prime 18 Pro. Firmware will become available at 'out/c10gx.sof'. 
+  2. Program device by JTAG or with Serial Flash Loader (see [1]).
+  3. Watch or/and measure frequency on LED #3, LED #4. It should be equal to 1Hz
 
 ## Links
 
-  1. [Application Note about using of Serial Flash Loader](https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an370.pdf)
+  1. TODO: link to serial flash loader firmware 

sfl.qpf c10gx.qpfsfl.qpf renamed to c10gx.qpf

@@ -1,12 +1,12 @@
 # -------------------------------------------------------------------------- #
 #
 # Copyright (C) 2018  Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
 # Subscription Agreement, the Intel Quartus Prime License Agreement,
 # the Intel FPGA IP License Agreement, or other applicable license
 # agreement, including, without limitation, that your use is for
@@ -18,13 +18,14 @@
 #
 # Quartus Prime
 # Version 18.0.0 Build 219 04/25/2018 SJ Pro Edition
-# Date created = 01:03:13  Май 08, 2018
+# Date created = 14:19:16  July 13, 2018
 #
 # -------------------------------------------------------------------------- #
 
 QUARTUS_VERSION = "18.0"
-DATE = "01:03:13  Май 08, 2018"
+DATE = "14:19:16  July 13, 2018"
 
 # Revisions
 
+PROJECT_REVISION = "c10gx"
 PROJECT_REVISION = "sfl"

sfl.qsf c10gx.qsfsfl.qsf renamed to c10gx.qsf

@@ -17,19 +17,32 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 ############## PROJECT FILES ##################
 
 set_global_assignment -name SYSTEMVERILOG_FILE main.sv
-set_global_assignment -name QIP_FILE sfl/sfl.qip
+set_global_assignment -name SDC_FILE c10gx.sdc
 
 ############## PIN ASSIGNMENTS ##################
 
-set_location_assignment PIN_AC13 -to clkusr_100m
+## Clocks
+
+### 100 MHz, single-ended
+set_location_assignment PIN_AC13 -to clk100
+set_instance_assignment -name IO_STANDARD "1.8 V" -to clk100 -entity main
+
+### 156.25 MHz, differential
+set_location_assignment PIN_U22 -to clk156p
+set_instance_assignment -name IO_STANDARD LVDS -to clk156p -entity main
+set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION AC_COUPLING -to clk156p -entity main
+set_instance_assignment -name OUTPUT_TERMINATION OCT_100_OHMS -to clk156p -entity main
+set_instance_assignment -name OUTPUT_TERMINATION OCT_100_OHMS -to "clk156p(n)" -entity main
+
+## LEDs
+
 set_location_assignment PIN_A2 -to led[3]
 set_location_assignment PIN_A3 -to led[4]
 set_location_assignment PIN_A4 -to led[5]
 set_location_assignment PIN_A6 -to led[6]
 set_location_assignment PIN_A8 -to led[7]
 set_location_assignment PIN_A9 -to led[8]
 
-set_instance_assignment -name IO_STANDARD "1.8 V" -to clkusr_100m -entity main
 set_instance_assignment -name IO_STANDARD "1.8 V" -to led[3] -entity main
 set_instance_assignment -name IO_STANDARD "1.8 V" -to led[4] -entity main
 set_instance_assignment -name IO_STANDARD "1.8 V" -to led[5] -entity main
@@ -39,14 +52,14 @@ set_instance_assignment -name IO_STANDARD "1.8 V" -to led[8] -entity main
 
 set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF
 
-
 ############## ADDED BY QUARTUS ##################
 
-set_global_assignment -name IP_FILE sfl.ip
 set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
 set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
 set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
 set_global_assignment -name GENERATE_PR_RBF_FILE OFF
 set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
 set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
+set_instance_assignment -name PARTITION_COLOUR 4288537343 -to main -entity main
+set_instance_assignment -name PARTITION_COLOUR 4291690369 -to auto_fab_0 -entity main

c10gx.sdc

@@ -0,0 +1,5 @@
+derive_pll_clocks
+derive_clock_uncertainty
+
+create_clock -period "156.250MHz"	[get_ports { clk156p }]
+create_clock -period "100.000MHz"	[get_ports { clk100 }]

main.sv

@@ -2,24 +2,39 @@
 // Intel / Altera Cyclone 10 GX board test project
 // General R&D, 2018
 
-module main(
+`define LED_100MHZ 3
+`define LED_156MHZ 4
+
+`define CLK_100MHZ 32'd100000000
+`define CLK_156MHZ 32'd156250000
 
-      input clkusr_100m,  // 100 MHz, single-ended
-      output [8:3]led
+module main(
+  input clk100,    // 100 MHz, single-ended
+  input clk156p,   // 156.25 MHz, diff pair 
+  output reg [8:3]led
 );
 
-/* Blink leds
+/* Blink leds from 100Mhz and 156Mhz references
  */
 logic [31:0] clk100_cntr;
-always_ff @(posedge clkusr_100m)
+logic [31:0] clk156_cntr;
+
+always_ff @(posedge clk100) begin
   clk100_cntr <= clk100_cntr + 1'b1;
+  if ( clk100_cntr == (`CLK_100MHZ/2 - 1) ) begin
+    led[`LED_100MHZ] <= ~led[`LED_100MHZ];
+    clk100_cntr <= 32'd0;
+  end
+end
 
-assign led[8:3] = clk100_cntr[29:24];
+always_ff @(posedge clk156p) begin
+  clk156_cntr <= clk156_cntr + 1'b1;
+  if ( clk156_cntr == (`CLK_156MHZ/2 - 1) ) begin
+    led[`LED_156MHZ] <= ~led[`LED_156MHZ];
+    clk156_cntr <= 32'd0;
+  end
+end
 
-/* Serial Flash Loader instance
- */
-sfl u0 (
-  .noe_in ( 1'b0 ) // 0 = enabled
-);
+assign led[8:`LED_156MHZ+1] = '0;
 
 endmodule