CUDA/HIP: optimize mmv paths taken for HIP/CDNA

Author: IMbackK

ggml/src/ggml-cuda/common.cuh

@@ -253,7 +253,11 @@ static bool fp16_mma_hardware_available(const int cc) {
 }
 
 static bool bf16_mma_hardware_available(const int cc) {
-    return GGML_CUDA_CC_IS_NVIDIA(cc) && cc >= GGML_CUDA_CC_AMPERE;
+    return GGML_CUDA_CC_IS_NVIDIA(cc) && cc >= GGML_CUDA_CC_AMPERE || GGML_CUDA_CC_IS_CDNA(cc) || cc >= GGML_CUDA_CC_RDNA3;
+}
+
+static bool fp32_mma_hardware_available(const int cc) {
+    return GGML_CUDA_CC_IS_CDNA(cc);
 }
 
 // Volta technically had FP16 tensor cores but they work very differently compared to Turing and later.

ggml/src/ggml-cuda/mmv.cu

@@ -456,6 +456,8 @@ bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_
                     return ne11 <= 4;
                 }
                 return ne11 <= 3;
+            } else if (fp32_mma_hardware_available(cc)) {
+                return ne11 <= 3;
             }
             return ne11 <= 8;
         case GGML_TYPE_F16:
@@ -468,6 +470,8 @@ bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_
                     return src0_small && ne11 <= 3;
                 }
                 return ne11 <= 8;
+            } else if (fp16_mma_hardware_available(cc)) {
+                return ne11 <= 2;
             }
             return ne11 <= 8;
         case GGML_TYPE_BF16:
@@ -480,6 +484,8 @@ bool ggml_cuda_should_use_mmv(enum ggml_type type, int cc, const int64_t * src0_
                     return src0_small && ne11 <= 3;
                 }
                 return ne11 <= 8;
+            } else if (bf16_mma_hardware_available(cc)) {
+                return ne11 <= 3;
             }
             return ne11 <= 8;
         default: