Skip to content

Commit 23ac112

Browse files
authored
Update index.md
1 parent 9d7d923 commit 23ac112

File tree

1 file changed

+1
-1
lines changed

1 file changed

+1
-1
lines changed

topics/Verilog/index.md

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
---
2-
aliases: hardware description language, HDL, verilog
2+
aliases: hdl, hardware-description-language
33
display_name: Verilog
44
short_description: Verilog is a hardware description language used to model electronic systems.
55
topic: Verilog

0 commit comments

Comments
 (0)