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1 parent ad0d84f commit 8a09dd3Copy full SHA for 8a09dd3
zjit/src/backend/arm64/mod.rs
@@ -202,9 +202,6 @@ impl Assembler
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const SCRATCH1: A64Opnd = A64Opnd::Reg(X17_REG);
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/// Get the list of registers from which we will allocate on this platform
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- /// These are caller-saved registers
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- /// Note: we intentionally exclude C_RET_REG (X0) from this list
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- /// because of the way it's used in gen_leave() and gen_leave_exit()
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pub fn get_alloc_regs() -> Vec<Reg> {
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ALLOC_REGS.to_vec()
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}
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