Skip to content

Commit 7ad7d6c

Browse files
committed
Update README.md
1 parent 41081b9 commit 7ad7d6c

File tree

1 file changed

+16
-0
lines changed

1 file changed

+16
-0
lines changed

README.md

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,22 @@
44

55
Full SystemVerilog IEEE 1800-2023 grammar for [tree-sitter](https://github.com/tree-sitter/tree-sitter).
66

7+
# Differences with [tree-sitter-verilog](https://github.com/tree-sitter/tree-sitter-verilog)
8+
9+
## Pros ##
10+
- Full implementation of the latest SystemVerilog standard (IEEE 1800-2023)
11+
- Robust and reliable
12+
- Actively maintained
13+
- Thoroughly tested (~2000 tests, including the whole UVM 2.0 and some open source projects)
14+
- Implements node fields
15+
- Supports parsing of code snippets (e.g., always block outside of a module)
16+
- Basic preprocessing capabilities
17+
- Currently used on Emacs `verilog-ts-mode` and `nvim systemverilog` plugin
18+
19+
## Cons
20+
- Generated parser is double the size
21+
- Generation of the compiled grammar takes longer (this only needs to be done once)
22+
723
## References
824

925
- https://en.wikipedia.org/wiki/Verilog

0 commit comments

Comments
 (0)