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[kernel][x86] refresh the intel microarchiture list with newer entries
Just an addition of a few more newer (and a couple we had missed before) to the list of intel microarchitectures. Nothing really new, except Raptor Lake and Tremont, which is pointed at the microarch just before it. Saltwell is added for completion, but it's unlikely the kernel will run properly on it since it's a x86-64-v1 core. Change-Id: I685b456d1689036e330618a351d660ee455bfea0 Reviewed-on: https://fuchsia-review.googlesource.com/c/fuchsia/+/762296 Reviewed-by: Venkatesh Srinivas <[email protected]> Reviewed-by: Joshua Seaton <[email protected]> Commit-Queue: Travis Geiselbrecht <[email protected]>
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‎zircon/kernel/arch/x86/feature.cc‎

Lines changed: 19 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -954,7 +954,9 @@ const x86_microarch_config_t* get_microarch_config(const cpu_id::CpuId* cpuid) {
954954
auto processor_id = cpuid->ReadProcessorId();
955955

956956
if (vendor.manufacturer() == cpu_id::ManufacturerInfo::INTEL && processor_id.family() == 0x6) {
957+
/* Table largely from https://en.wikichip.org/wiki/intel/cpuid */
957958
switch (processor_id.model()) {
959+
/* Big cores */
958960
case 0x1a: /* Nehalem */
959961
case 0x1e: /* Nehalem */
960962
case 0x1f: /* Nehalem */
@@ -982,32 +984,45 @@ const x86_microarch_config_t* get_microarch_config(const cpu_id::CpuId* cpuid) {
982984
return &broadwell_config;
983985
case 0x4e: /* Skylake Y/U */
984986
case 0x5e: /* Skylake H/S */
985-
case 0x8e: /* Kaby Lake Y/U, Coffee Lake, Whiskey Lake */
987+
case 0x8e: /* Kaby Lake Y/U, Coffee Lake, Whiskey Lake, Amber Lake, Comet Lake U */
986988
case 0x9e: /* Kaby Lake H/S, Coffee Lake, Whiskey Lake */
989+
case 0xa5: /* Comet Lake S/H */
987990
return &skylake_config;
988991
case 0x55: /* Skylake X/SP, Cascade Lake */
989992
return &skylake_x_config;
990993
case 0x66: /* Cannon Lake U */
991994
return &cannon_lake_config;
992995
case 0x6a: /* Ice Lake-SP */
996+
case 0x6c: /* Ice Lake-DE */
997+
case 0x7d: /* Ice Lake Y */
998+
case 0x7e: /* Ice Lake U */
993999
return &icelake_config;
9941000
case 0x8c: /* Tiger Lake UP */
9951001
case 0x8d: /* Tiger Lake H */
1002+
case 0xa7: /* Rocket Lake S */
9961003
return &tiger_lake_config;
9971004
case 0x97: /* Alder Lake S */
9981005
case 0x9a: /* Alder Lake H/P/U */
1006+
case 0xb7: /* Raptor Lake S */
9991007
return &alder_lake_config;
1008+
1009+
/* Small cores */
10001010
case 0x37: /* Silvermont */
10011011
case 0x4a: /* Silvermont "Cherry View" */
1002-
case 0x4d: /* Silvermont "Avoton" */
1003-
case 0x4c: /* Airmont "Braswell" */
1004-
case 0x5a: /* Airmont */
1012+
case 0x4d: /* Silvermont "Avoton", "Rangeley" */
1013+
case 0x5a: /* Silvermont "Anniedale" */
1014+
case 0x5d: /* Silvermont "SoFIA" */
1015+
case 0x4c: /* Airmont "Braswell", "Cherry Trail" */
10051016
return &silvermont_config;
10061017
case 0x5c: /* Goldmont (Apollo Lake) */
10071018
case 0x5f: /* Goldmont (Denverton) */
10081019
return &goldmont_config;
10091020
case 0x7a: /* Goldmont Plus (Gemini Lake) */
1021+
case 0x8a: /* Tremont (Lakefield) */
1022+
case 0x96: /* Tremont (Elkhart Lake) */
1023+
case 0x9c: /* Tremont (Jasper Lake) */
10101024
return &goldmont_plus_config;
1025+
10111026
default:
10121027
return &intel_default_config;
10131028
}

‎zircon/kernel/lib/arch/cpuid.cc‎

Lines changed: 65 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -99,8 +99,12 @@ std::string_view ToString(Microarchitecture microarch) {
9999
return "Intel Tiger Lake";
100100
case Microarchitecture::kIntelAlderLake:
101101
return "Intel Alder Lake";
102+
case Microarchitecture::kIntelRaptorLake:
103+
return "Intel Raptor Lake";
102104
case Microarchitecture::kIntelBonnell:
103105
return "Intel Bonnell";
106+
case Microarchitecture::kIntelSaltwell:
107+
return "Intel Saltwell";
104108
case Microarchitecture::kIntelSilvermont:
105109
return "Intel Silvermont";
106110
case Microarchitecture::kIntelAirmont:
@@ -142,80 +146,90 @@ uint8_t CpuidVersionInfo::model() const {
142146
Microarchitecture CpuidVersionInfo::microarchitecture(Vendor vendor) const {
143147
switch (vendor) {
144148
case Vendor::kIntel: {
149+
// Table largely from https://en.wikichip.org/wiki/intel/cpuid
145150
switch (family()) {
146151
case 0x6: {
147152
switch (model()) {
148-
case 0x0f: // Merom.
149-
case 0x16: // Merom L.
150-
case 0x17: // Penryn, Wolfdale, Yorkfield, Harpertown, QC.
151-
case 0x1d: // Dunnington.
153+
// Big cores
154+
case 0x0f: // Merom
155+
case 0x16: // Merom L
156+
case 0x17: // Penryn, Wolfdale, Yorkfield, Harpertown, QC
157+
case 0x1d: // Dunnington
152158
return Microarchitecture::kIntelCore2;
153-
case 0x1a: // Bloomfield, EP, WS.
154-
case 0x1e: // Lynnfield, Clarksfield.
155-
case 0x1f: // Auburndale, Havendale.
156-
case 0x2e: // EX.
159+
case 0x1a: // Bloomfield, EP, WS
160+
case 0x1e: // Lynnfield, Clarksfield
161+
case 0x1f: // Auburndale, Havendale
162+
case 0x2e: // EX
157163
return Microarchitecture::kIntelNehalem;
158-
case 0x25: // Arrandale, Clarkdale.
159-
case 0x2c: // Gulftown, EP.
160-
case 0x2f: // EX.
164+
case 0x25: // Arrandale, Clarkdale
165+
case 0x2c: // Gulftown, EP
166+
case 0x2f: // EX
161167
return Microarchitecture::kIntelWestmere;
162-
case 0x2a: // M, H.
163-
case 0x2d: // E, EN, EP.
168+
case 0x2a: // M, H
169+
case 0x2d: // E, EN, EP
164170
return Microarchitecture::kIntelSandyBridge;
165171
case 0x3a: // M, H, Gladden
166-
case 0x3e: // E, EN, EP, EX.
172+
case 0x3e: // E, EN, EP, EX
167173
return Microarchitecture::kIntelIvyBridge;
168-
case 0x3c: // S.
169-
case 0x3f: // E, EP, EX.
170-
case 0x45: // ULT.
171-
case 0x46: // GT3E.
174+
case 0x3c: // S
175+
case 0x3f: // E, EP, EX
176+
case 0x45: // ULT
177+
case 0x46: // GT3E
172178
return Microarchitecture::kIntelHaswell;
173-
case 0x3d: // U, Y, S.
174-
case 0x47: // H, C, W.
175-
case 0x56: // DE, Hewitt Lake.
176-
case 0x4f: // E, EP, EX.
179+
case 0x3d: // U, Y, S
180+
case 0x47: // H, C, W
181+
case 0x56: // DE, Hewitt Lake
182+
case 0x4f: // E, EP, EX
177183
return Microarchitecture::kIntelBroadwell;
178-
case 0x4e: // Skylake Y, U.
179-
case 0x5e: // Skylake DT, H, S.
180-
// Kaby Lake Y, U; Coffee Lake U; Whiskey Lake U; Amber Lake Y;
181-
// Comet Lake U.
182-
case 0x8e:
183-
// Kaby Lake T, H, S, X; Coffee Lake S, H, E; Comet Lake S, H.
184-
case 0x9e:
184+
case 0x4e: // Skylake Y, U
185+
case 0x5e: // Skylake DT, H, S
186+
case 0x8e: // Kaby Lake Y, U; Coffee Lake U; Whiskey Lake U; Amber Lake Y;
187+
// Comet Lake U
188+
case 0x9e: // Kaby Lake T, H, S, X; Coffee Lake S, H, E
189+
case 0xa5: // Comet Lake S, H
185190
return Microarchitecture::kIntelSkylake;
186-
// Skylake SP, X, DE, W; Cascade Lake SP, X, W; Cooper Lake.
187-
case 0x55:
191+
case 0x55: // Skylake SP, X, DE, W; Cascade Lake SP, X, W; Cooper Lake
188192
return Microarchitecture::kIntelSkylakeServer;
189-
case 0x66: // U.
193+
case 0x66: // Cannon Lake U
190194
return Microarchitecture::kIntelCannonLake;
191-
case 0x6a:
195+
case 0x6a: // Ice Lake Server SP
196+
case 0x6c: // Ice Lake Server DE
197+
case 0x7d: // Ice Lake Y
198+
case 0x7e: // Ice Lake U
192199
return Microarchitecture::kIntelIceLake;
193-
case 0x8c: // Tiger Lake UP.
194-
case 0x8d: // Tiger Lake H.
200+
case 0x8c: // Tiger Lake UP
201+
case 0x8d: // Tiger Lake H
195202
return Microarchitecture::kIntelTigerLake;
196203
case 0x97: // Alder Lake S
197204
case 0x9a: // Alder Lake H, P, U
198205
return Microarchitecture::kIntelAlderLake;
199-
case 0x1c: // Silverthorne, Diamondville, Pineview.
200-
case 0x26: // Lincroft.
201-
case 0x27: // Penwell.
202-
case 0x35: // Cloverview.
203-
case 0x36: // Cedarview.
206+
case 0xb7: // Raptor Lake S
207+
return Microarchitecture::kIntelRaptorLake;
208+
209+
// Small cores
210+
case 0x1c: // Silverthorne, Diamondville, Pineview
211+
case 0x26: // Lincroft
204212
return Microarchitecture::kIntelBonnell;
205-
case 0x37: // Bay Trail.
206-
case 0x4a: // Tangier.
207-
case 0x4d: // Avoton, Rangeley.
208-
case 0x5a: // Anniedale.
209-
case 0x5d: // SoFIA.
213+
case 0x27: // Penwell
214+
case 0x35: // Cloverview
215+
case 0x36: // Cedarview
216+
return Microarchitecture::kIntelSaltwell;
217+
case 0x37: // Bay Trail
218+
case 0x4a: // Tangier
219+
case 0x4d: // Avoton, Rangeley
220+
case 0x5a: // Anniedale
221+
case 0x5d: // SoFIA
210222
return Microarchitecture::kIntelSilvermont;
211-
case 0x4c: // Cherry Trail, Braswell.
223+
case 0x4c: // Cherry Trail, Braswell
212224
return Microarchitecture::kIntelAirmont;
213-
case 0x5c: // Apollo Lake, Broxton.
214-
case 0x5f: // Denverton.
225+
case 0x5c: // Apollo Lake, Broxton
226+
case 0x5f: // Denverton
215227
return Microarchitecture::kIntelGoldmont;
216-
case 0x7a: // Gemini Lake.
228+
case 0x7a: // Gemini Lake
217229
return Microarchitecture::kIntelGoldmontPlus;
218-
case 0x86: // Elkhart Lake.
230+
case 0x8a: // Lakefield
231+
case 0x96: // Elkhart Lake
232+
case 0x9c: // Jasper Lake
219233
return Microarchitecture::kIntelTremont;
220234
}
221235
return Microarchitecture::kUnknown;
@@ -224,6 +238,7 @@ Microarchitecture CpuidVersionInfo::microarchitecture(Vendor vendor) const {
224238
return Microarchitecture::kUnknown;
225239
}
226240
case Vendor::kAmd: {
241+
// Table largely from https://en.wikichip.org/wiki/amd/cpuid
227242
switch (family()) {
228243
case 0x15: // Bulldozer/Piledriver/Steamroller/Excavator
229244
return Microarchitecture::kAmdFamilyBulldozer;

‎zircon/kernel/lib/arch/include/lib/arch/x86/bug.h‎

Lines changed: 41 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,9 @@ inline bool HasX86MdsBugs(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
150150
return true;
151151
case Microarchitecture::kIntelTigerLake:
152152
case Microarchitecture::kIntelAlderLake:
153+
case Microarchitecture::kIntelRaptorLake:
153154
case Microarchitecture::kIntelBonnell:
155+
case Microarchitecture::kIntelSaltwell:
154156
case Microarchitecture::kIntelGoldmont:
155157
case Microarchitecture::kIntelGoldmontPlus:
156158
case Microarchitecture::kIntelTremont:
@@ -194,7 +196,9 @@ inline bool HasX86TaaBug(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
194196
case Microarchitecture::kIntelIvyBridge:
195197
case Microarchitecture::kIntelTigerLake:
196198
case Microarchitecture::kIntelAlderLake:
199+
case Microarchitecture::kIntelRaptorLake:
197200
case Microarchitecture::kIntelBonnell:
201+
case Microarchitecture::kIntelSaltwell:
198202
case Microarchitecture::kIntelSilvermont:
199203
case Microarchitecture::kIntelAirmont:
200204
case Microarchitecture::kIntelGoldmont:
@@ -255,7 +259,7 @@ inline bool HasX86SsbBug(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
255259
case Microarchitecture::kIntelIceLake:
256260
case Microarchitecture::kIntelTigerLake:
257261
case Microarchitecture::kIntelAlderLake:
258-
case Microarchitecture::kIntelBonnell:
262+
case Microarchitecture::kIntelRaptorLake:
259263
case Microarchitecture::kIntelGoldmont:
260264
case Microarchitecture::kIntelGoldmontPlus:
261265
case Microarchitecture::kIntelTremont:
@@ -264,6 +268,8 @@ inline bool HasX86SsbBug(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
264268
case Microarchitecture::kAmdFamilyZen:
265269
case Microarchitecture::kAmdFamilyZen3:
266270
return true;
271+
case Microarchitecture::kIntelBonnell:
272+
case Microarchitecture::kIntelSaltwell:
267273
case Microarchitecture::kIntelSilvermont:
268274
case Microarchitecture::kIntelAirmont:
269275
break;
@@ -346,22 +352,38 @@ inline bool HasX86MeltdownBug(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
346352
case Microarchitecture::kIntelBroadwell:
347353
case Microarchitecture::kIntelSkylake:
348354
case Microarchitecture::kIntelCannonLake:
349-
case Microarchitecture::kIntelBonnell:
350-
case Microarchitecture::kIntelSilvermont:
351-
case Microarchitecture::kIntelAirmont:
352355
return true;
353-
case Microarchitecture::kIntelSkylakeServer:
354356
case Microarchitecture::kIntelIceLake:
355357
case Microarchitecture::kIntelTigerLake:
356358
case Microarchitecture::kIntelAlderLake:
359+
case Microarchitecture::kIntelRaptorLake:
360+
case Microarchitecture::kIntelBonnell:
361+
case Microarchitecture::kIntelSaltwell:
362+
case Microarchitecture::kIntelSilvermont:
363+
case Microarchitecture::kIntelAirmont:
357364
case Microarchitecture::kIntelGoldmont:
358-
case Microarchitecture::kIntelGoldmontPlus:
359365
case Microarchitecture::kIntelTremont:
360366
case Microarchitecture::kAmdFamilyBulldozer:
361367
case Microarchitecture::kAmdFamilyJaguar:
362368
case Microarchitecture::kAmdFamilyZen:
363369
case Microarchitecture::kAmdFamilyZen3:
364370
break;
371+
// Special cases from the above table.
372+
case Microarchitecture::kIntelSkylakeServer: {
373+
const auto info = cpuid.template Read<CpuidVersionInfo>();
374+
if (info.stepping() >= 0x6) { // Cascade Lake server+
375+
return false;
376+
}
377+
return true; // Skylake server
378+
break;
379+
}
380+
case Microarchitecture::kIntelGoldmontPlus: {
381+
const auto info = cpuid.template Read<CpuidVersionInfo>();
382+
if (info.stepping() == 0x1) { // First stepping was suceptable to Meltdown.
383+
return true;
384+
}
385+
break;
386+
}
365387
}
366388
return false;
367389
}
@@ -390,12 +412,13 @@ inline bool HasX86L1tfBug(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
390412
case Microarchitecture::kIntelBroadwell:
391413
case Microarchitecture::kIntelSkylake:
392414
case Microarchitecture::kIntelCannonLake:
393-
case Microarchitecture::kIntelIceLake:
394-
case Microarchitecture::kIntelBonnell:
395415
return true;
396-
case Microarchitecture::kIntelSkylakeServer:
416+
case Microarchitecture::kIntelIceLake:
397417
case Microarchitecture::kIntelTigerLake:
398418
case Microarchitecture::kIntelAlderLake:
419+
case Microarchitecture::kIntelRaptorLake:
420+
case Microarchitecture::kIntelBonnell:
421+
case Microarchitecture::kIntelSaltwell:
399422
case Microarchitecture::kIntelSilvermont:
400423
case Microarchitecture::kIntelAirmont:
401424
case Microarchitecture::kIntelGoldmont:
@@ -406,6 +429,15 @@ inline bool HasX86L1tfBug(CpuidIoProvider&& cpuid, MsrIoProvider&& msr) {
406429
case Microarchitecture::kAmdFamilyZen:
407430
case Microarchitecture::kAmdFamilyZen3:
408431
break;
432+
// Special cases from the above table.
433+
case Microarchitecture::kIntelSkylakeServer: {
434+
const auto info = cpuid.template Read<CpuidVersionInfo>();
435+
if (info.stepping() >= 0x6) { // Cascade Lake server+
436+
return false;
437+
}
438+
return true; // Skylake server
439+
break;
440+
}
409441
}
410442
return false;
411443
}

‎zircon/kernel/lib/arch/include/lib/arch/x86/cpuid.h‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -115,9 +115,11 @@ enum class Microarchitecture {
115115
kIntelIceLake,
116116
kIntelTigerLake,
117117
kIntelAlderLake,
118+
kIntelRaptorLake,
118119

119120
// Intel Atom family.
120121
kIntelBonnell,
122+
kIntelSaltwell,
121123
kIntelSilvermont,
122124
kIntelAirmont,
123125
kIntelGoldmont,
@@ -497,7 +499,8 @@ struct CpuidExtendedFeatureFlagsC
497499
// Bit 24 is reserved.
498500
DEF_BIT(23, kl);
499501
DEF_BIT(22, rdpid);
500-
// Bits [21:17] are 'The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.'
502+
// Bits [21:17] are 'The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit
503+
// mode.'
501504
DEF_BIT(16, la57);
502505
// Bit 15 is reserved.
503506
DEF_BIT(14, avx512_vpopcntdq);

‎zircon/kernel/lib/arch/lbr.cc‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,7 @@ size_t LbrStack::Size(Microarchitecture microarch) {
117117
case Microarchitecture::kIntelCore2:
118118
return 4;
119119
case Microarchitecture::kIntelBonnell:
120+
case Microarchitecture::kIntelSaltwell:
120121
case Microarchitecture::kIntelSilvermont:
121122
case Microarchitecture::kIntelAirmont:
122123
return 8;
@@ -133,6 +134,7 @@ size_t LbrStack::Size(Microarchitecture microarch) {
133134
case Microarchitecture::kIntelIceLake:
134135
case Microarchitecture::kIntelTigerLake:
135136
case Microarchitecture::kIntelAlderLake:
137+
case Microarchitecture::kIntelRaptorLake:
136138
case Microarchitecture::kIntelGoldmont:
137139
case Microarchitecture::kIntelGoldmontPlus:
138140
case Microarchitecture::kIntelTremont:
@@ -148,6 +150,7 @@ bool LbrStack::SupportsCallstackProfiling(Microarchitecture microarch) {
148150
case Microarchitecture::kUnknown:
149151
case Microarchitecture::kIntelCore2:
150152
case Microarchitecture::kIntelBonnell:
153+
case Microarchitecture::kIntelSaltwell:
151154
case Microarchitecture::kIntelSilvermont:
152155
case Microarchitecture::kIntelAirmont:
153156
case Microarchitecture::kIntelNehalem:
@@ -167,6 +170,7 @@ bool LbrStack::SupportsCallstackProfiling(Microarchitecture microarch) {
167170
case Microarchitecture::kIntelIceLake:
168171
case Microarchitecture::kIntelTigerLake:
169172
case Microarchitecture::kIntelAlderLake:
173+
case Microarchitecture::kIntelRaptorLake:
170174
case Microarchitecture::kIntelGoldmont:
171175
case Microarchitecture::kIntelGoldmontPlus:
172176
case Microarchitecture::kIntelTremont:

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