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ladyadaladyada
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re-fix xtalless, add cache & freq fix
1 parent 2617090 commit ec04c6a

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2 files changed

+144
-136
lines changed

2 files changed

+144
-136
lines changed

‎boards.txt

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -324,12 +324,12 @@ adafruit_itsybitsy_m4.upload.use_1200bps_touch=true
324324
adafruit_itsybitsy_m4.upload.wait_for_upload_port=true
325325
adafruit_itsybitsy_m4.upload.native_usb=true
326326
adafruit_itsybitsy_m4.build.mcu=cortex-m4
327-
adafruit_itsybitsy_m4.build.f_cpu=48000000L
327+
adafruit_itsybitsy_m4.build.f_cpu=120000000L
328328
adafruit_itsybitsy_m4.build.usb_product="Adafruit ItsyBitsy M4"
329329
adafruit_itsybitsy_m4.build.usb_manufacturer="Adafruit LLC"
330330
adafruit_itsybitsy_m4.build.board=ITSYBITSY_M4
331331
adafruit_itsybitsy_m4.build.core=arduino
332-
adafruit_itsybitsy_m4.build.extra_flags=-D__SAMD51G19A__ -D__SAMD51__ {build.usb_flags} -D__FPU_PRESENT -DARM_MATH_CM4 -DCRYSTALLESS -mfloat-abi=hard -mfpu=fpv4-sp-d16
332+
adafruit_itsybitsy_m4.build.extra_flags=-D__SAMD51G19A__ -DADAFRUIT_ITSYBITSY_M4_EXPRESS -D__SAMD51__ {build.usb_flags} -D__FPU_PRESENT -DARM_MATH_CM4 -DCRYSTALLESS -mfloat-abi=hard -mfpu=fpv4-sp-d16
333333
adafruit_itsybitsy_m4.build.ldscript=linker_scripts/gcc/flash_with_bootloader.ld
334334
adafruit_itsybitsy_m4.build.openocdscript=openocd_scripts/arduino_zero.cfg
335335
adafruit_itsybitsy_m4.build.variant=itsybitsy_m4
@@ -339,6 +339,10 @@ adafruit_itsybitsy_m4.build.pid=0x802B
339339
adafruit_itsybitsy_m4.bootloader.tool=openocd
340340
adafruit_itsybitsy_m4.bootloader.file=metroM4/bootloader.bin
341341
adafruit_itsybitsy_m4.compiler.arm.cmsis.ldflags="-L{build.variant.path}" -larm_cortexM4lf_math -mfloat-abi=hard -mfpu=fpv4-sp-d16
342+
adafruit_itsybitsy_m4.menu.cache.on=Enabled
343+
adafruit_itsybitsy_m4.menu.cache.on.build.cache_flags=-DENABLE_CACHE
344+
adafruit_itsybitsy_m4.menu.cache.off=Disabled
345+
adafruit_itsybitsy_m4.menu.cache.off.build.cache_flags=
342346

343347

344348
# Adafruit Feather M4 (SAMD51)

‎cores/arduino/startup.c

Lines changed: 138 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -57,197 +57,201 @@ void SystemInit( void )
5757
#if defined(__SAMD51__)
5858
NVMCTRL->CTRLA.reg |= NVMCTRL_CTRLA_RWS(0);
5959

60-
#if defined(CRYSTALLESS)
61-
62-
63-
#else // has crystal
64-
65-
/* ----------------------------------------------------------------------------------------------
66-
* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
67-
*/
60+
#ifndef CRYSTALLESS
61+
/* ----------------------------------------------------------------------------------------------
62+
* 1) Enable XOSC32K clock (External on-board 32.768Hz oscillator)
63+
*/
64+
65+
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE | OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_CGM_XT | OSC32KCTRL_XOSC32K_XTALEN;
66+
67+
while( (OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) == 0 ){
68+
/* Wait for oscillator to be ready */
69+
}
6870

69-
OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE | OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_EN32K | OSC32KCTRL_XOSC32K_CGM_XT | OSC32KCTRL_XOSC32K_XTALEN;
70-
71-
while( (OSC32KCTRL->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) == 0 ){
72-
/* Wait for oscillator to be ready */
73-
}
71+
#endif //CRYSTALLESS
7472

75-
#endif //CRYSTALLESS
76-
7773
//software reset
7874

7975
GCLK->CTRLA.bit.SWRST = 1;
8076
while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST ){
8177
/* wait for reset to complete */
8278
}
79+
80+
#ifndef CRYSTALLESS
81+
/* ----------------------------------------------------------------------------------------------
82+
* 2) Put XOSC32K as source of Generic Clock Generator 3
83+
*/
84+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC32K) | //generic clock gen 3
85+
GCLK_GENCTRL_GENEN;
86+
#else
87+
/* ----------------------------------------------------------------------------------------------
88+
* 2) Put OSCULP32K as source of Generic Clock Generator 3
89+
*/
90+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN; //generic clock gen 3
91+
#endif
8392

84-
/* ----------------------------------------------------------------------------------------------
85-
* 2) Put XOSC32K as source of Generic Clock Generator 3
86-
*/
87-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_XOSC32K].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_XOSC32K) | //generic clock gen 3
88-
GCLK_GENCTRL_GENEN;
8993

90-
while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3 ){
91-
/* Wait for synchronization */
92-
}
94+
while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3 ){
95+
/* Wait for synchronization */
96+
}
9397

94-
/* ----------------------------------------------------------------------------------------------
95-
* 3) Put Generic Clock Generator 3 as source for Generic Clock Gen 0 (DFLL48M reference)
96-
*/
97-
GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
98-
99-
/* ----------------------------------------------------------------------------------------------
100-
* 4) Enable DFLL48M clock
101-
*/
98+
/* ----------------------------------------------------------------------------------------------
99+
* 3) Put Generic Clock Generator 3 as source for Generic Clock Gen 0 (DFLL48M reference)
100+
*/
101+
GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSCULP32K) | GCLK_GENCTRL_GENEN;
102+
103+
/* ----------------------------------------------------------------------------------------------
104+
* 4) Enable DFLL48M clock
105+
*/
102106

103107
while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0 ){
104108
/* Wait for synchronization */
105109
}
106110

107-
/* DFLL Configuration in Open Loop mode */
108-
109-
OSCCTRL->DFLLCTRLA.reg = 0;
110-
//GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK3_Val);
111-
112-
OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP( 0x1 ) |
113-
OSCCTRL_DFLLMUL_FSTEP( 0x1 ) |
114-
OSCCTRL_DFLLMUL_MUL( 0 );
115-
116-
while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLMUL )
117-
{
118-
/* Wait for synchronization */
119-
}
111+
/* DFLL Configuration in Open Loop mode */
120112

121-
OSCCTRL->DFLLCTRLB.reg = 0;
122-
while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLCTRLB )
123-
{
124-
/* Wait for synchronization */
125-
}
113+
OSCCTRL->DFLLCTRLA.reg = 0;
114+
//GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK3_Val);
126115

127-
OSCCTRL->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
128-
while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_ENABLE )
129-
{
130-
/* Wait for synchronization */
131-
}
132-
133-
OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg;
134-
while( OSCCTRL->DFLLSYNC.bit.DFLLVAL );
116+
OSCCTRL->DFLLMUL.reg = OSCCTRL_DFLLMUL_CSTEP( 0x1 ) |
117+
OSCCTRL_DFLLMUL_FSTEP( 0x1 ) |
118+
OSCCTRL_DFLLMUL_MUL( 0 );
119+
120+
while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLMUL )
121+
{
122+
/* Wait for synchronization */
123+
}
124+
125+
OSCCTRL->DFLLCTRLB.reg = 0;
126+
while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_DFLLCTRLB )
127+
{
128+
/* Wait for synchronization */
129+
}
130+
131+
OSCCTRL->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE;
132+
while ( OSCCTRL->DFLLSYNC.reg & OSCCTRL_DFLLSYNC_ENABLE )
133+
{
134+
/* Wait for synchronization */
135+
}
136+
137+
OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg;
138+
while( OSCCTRL->DFLLSYNC.bit.DFLLVAL );
135139

136140
OSCCTRL->DFLLCTRLB.reg = OSCCTRL_DFLLCTRLB_WAITLOCK |
137141
OSCCTRL_DFLLCTRLB_CCDIS | OSCCTRL_DFLLCTRLB_USBCRM ;
138142

139-
while ( !OSCCTRL->STATUS.bit.DFLLRDY )
140-
{
141-
/* Wait for synchronization */
142-
}
143-
144-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_1M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
145-
146-
while ( GCLK->SYNCBUSY.bit.GENCTRL5 ){
147-
/* Wait for synchronization */
148-
}
149-
143+
while ( !OSCCTRL->STATUS.bit.DFLLRDY )
144+
{
145+
/* Wait for synchronization */
146+
}
147+
148+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_1M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_DIV(24u);
149+
150+
while ( GCLK->SYNCBUSY.bit.GENCTRL5 ){
151+
/* Wait for synchronization */
152+
}
153+
150154

151155
/* ------------------------------------------------------------------------
152156
* Set up the PLLs
153157
*/
154158

155-
//PLL0 is 120MHz
156-
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
157-
158-
OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59); //120 Mhz
159-
160-
while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
161-
162-
//MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
163-
OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
164-
165-
OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
166-
167-
while( OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0 );
168-
169-
//PLL1 is 100MHz
170-
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
171-
172-
OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(49); //100 Mhz
173-
174-
while(OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.DPLLRATIO);
175-
176-
//MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
177-
OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
178-
179-
OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
180-
181-
while( OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK == 0 );
182-
159+
//PLL0 is 120MHz
160+
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
161+
162+
OSCCTRL->Dpll[0].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(59); //120 Mhz
163+
164+
while(OSCCTRL->Dpll[0].DPLLSYNCBUSY.bit.DPLLRATIO);
165+
166+
//MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
167+
OSCCTRL->Dpll[0].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
168+
169+
OSCCTRL->Dpll[0].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
170+
171+
while( OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK == 0 );
172+
173+
//PLL1 is 100MHz
174+
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].reg = (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK5_Val);
175+
176+
OSCCTRL->Dpll[1].DPLLRATIO.reg = OSCCTRL_DPLLRATIO_LDRFRAC(0x00) | OSCCTRL_DPLLRATIO_LDR(49); //100 Mhz
177+
178+
while(OSCCTRL->Dpll[1].DPLLSYNCBUSY.bit.DPLLRATIO);
179+
180+
//MUST USE LBYPASS DUE TO BUG IN REV A OF SAMD51
181+
OSCCTRL->Dpll[1].DPLLCTRLB.reg = OSCCTRL_DPLLCTRLB_REFCLK_GCLK | OSCCTRL_DPLLCTRLB_LBYPASS;
182+
183+
OSCCTRL->Dpll[1].DPLLCTRLA.reg = OSCCTRL_DPLLCTRLA_ENABLE;
184+
185+
while( OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY == 0 || OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK == 0 );
186+
183187

184188
/* ------------------------------------------------------------------------
185189
* Set up the peripheral clocks
186190
*/
187191

188192
//48MHZ CLOCK FOR USB AND STUFF
189193
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_48M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
190-
GCLK_GENCTRL_IDC |
191-
//GCLK_GENCTRL_OE |
192-
GCLK_GENCTRL_GENEN;
193-
194-
while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_48M_SYNC)
195-
{
196-
/* Wait for synchronization */
197-
}
198-
199-
//100MHZ CLOCK FOR OTHER PERIPHERALS
200-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_100M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL1_Val) |
201-
GCLK_GENCTRL_IDC |
202-
//GCLK_GENCTRL_OE |
203-
GCLK_GENCTRL_GENEN;
204-
205-
while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_100M_SYNC)
206-
{
207-
/* Wait for synchronization */
208-
}
209-
194+
GCLK_GENCTRL_IDC |
195+
//GCLK_GENCTRL_OE |
196+
GCLK_GENCTRL_GENEN;
197+
198+
while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_48M_SYNC)
199+
{
200+
/* Wait for synchronization */
201+
}
202+
203+
//100MHZ CLOCK FOR OTHER PERIPHERALS
204+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_100M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DPLL1_Val) |
205+
GCLK_GENCTRL_IDC |
206+
//GCLK_GENCTRL_OE |
207+
GCLK_GENCTRL_GENEN;
208+
209+
while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_100M_SYNC)
210+
{
211+
/* Wait for synchronization */
212+
}
213+
210214
//12MHZ CLOCK FOR DAC
211-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_12M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
215+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_12M].reg = GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_DFLL_Val) |
212216
GCLK_GENCTRL_IDC |
213217
GCLK_GENCTRL_DIV(4) |
214218
GCLK_GENCTRL_DIVSEL |
215219
//GCLK_GENCTRL_OE |
216220
GCLK_GENCTRL_GENEN;
217-
218-
while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_12M_SYNC)
221+
222+
while ( GCLK->SYNCBUSY.reg & GENERIC_CLOCK_GENERATOR_12M_SYNC)
219223
{
220-
/* Wait for synchronization */
224+
/* Wait for synchronization */
221225
}
222226

223227
/*---------------------------------------------------------------------
224-
* Set up main clock
225-
*/
226-
227-
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_MAIN].reg = GCLK_GENCTRL_SRC(MAIN_CLOCK_SOURCE) |
228-
GCLK_GENCTRL_IDC |
229-
//GCLK_GENCTRL_OE |
230-
GCLK_GENCTRL_GENEN;
231-
228+
* Set up main clock
229+
*/
230+
231+
GCLK->GENCTRL[GENERIC_CLOCK_GENERATOR_MAIN].reg = GCLK_GENCTRL_SRC(MAIN_CLOCK_SOURCE) |
232+
GCLK_GENCTRL_IDC |
233+
//GCLK_GENCTRL_OE |
234+
GCLK_GENCTRL_GENEN;
235+
232236

233237
while ( GCLK->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0 )
234-
{
235-
/* Wait for synchronization */
236-
}
238+
{
239+
/* Wait for synchronization */
240+
}
237241

238242
MCLK->CPUDIV.reg = MCLK_CPUDIV_DIV_DIV1;
239-
243+
240244
/* Use the LDO regulator by default */
241245
SUPC->VREG.bit.SEL = 0;
242246

243-
247+
244248
/* If desired, enable cache! */
245249
#if defined(ENABLE_CACHE)
246250
__disable_irq();
247251
CMCC->CTRL.reg = 1;
248252
__enable_irq();
249253
#endif
250-
254+
251255
//*************** END SAMD51 *************************//
252256

253257
#else

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