@@ -8,5 +8,43 @@ package cpu
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const cacheLineSize = 64
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+ // Bit fields for CPUCFG registers, Related reference documents:
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+ // https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg
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+ const (
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+ // CPUCFG1 bits
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+ cpucfg1_CRC32 = 1 << 25
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+
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+ // CPUCFG2 bits
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+ cpucfg2_LAM_BH = 1 << 27
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+ cpucfg2_LAMCAS = 1 << 28
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+ )
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+
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func initOptions () {
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+ options = []option {
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+ {Name : "lsx" , Feature : & Loong64 .HasLSX },
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+ {Name : "lasx" , Feature : & Loong64 .HasLASX },
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+ {Name : "crc32" , Feature : & Loong64 .HasCRC32 },
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+ {Name : "lam_bh" , Feature : & Loong64 .HasLAM_BH },
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+ {Name : "lamcas" , Feature : & Loong64 .HasLAMCAS },
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+ }
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+
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+ // The CPUCFG data on Loong64 only reflects the hardware capabilities,
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+ // not the kernel support status, so features such as LSX and LASX that
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+ // require kernel support cannot be obtained from the CPUCFG data.
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+ //
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+ // These features only require hardware capability support and do not
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+ // require kernel specific support, so they can be obtained directly
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+ // through CPUCFG
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+ cfg1 := get_cpucfg (1 )
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+ cfg2 := get_cpucfg (2 )
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+
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+ Loong64 .HasCRC32 = cfgIsSet (cfg1 , cpucfg1_CRC32 )
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+ Loong64 .HasLAMCAS = cfgIsSet (cfg2 , cpucfg2_LAMCAS )
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+ Loong64 .HasLAM_BH = cfgIsSet (cfg2 , cpucfg2_LAM_BH )
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+ }
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+
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+ func get_cpucfg (reg uint32 ) uint32
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+
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+ func cfgIsSet (cfg uint32 , val uint32 ) bool {
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+ return cfg & val != 0
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}
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