@@ -144,7 +144,7 @@ define arm_aapcs_vfpcc <1 x i64> @vmov_i64_b() {
144144;
145145; CHECK-BE-LABEL: vmov_i64_b:
146146; CHECK-BE: @ %bb.0:
147- ; CHECK-BE-NEXT: d16, #0xff0000ff00ffff00
147+ ; CHECK-BE-NEXT: vmov.i64 d16, #0xff0000ff00ffff00
148148; CHECK-BE-NEXT: vrev64.32 d0, d16
149149; CHECK-BE-NEXT: bx lr
150150 ret <1 x i64 > <i64 72056498804490495 >
@@ -180,7 +180,7 @@ define arm_aapcs_vfpcc <2 x i64> @and_v2i64_b(<2 x i64> %a) {
180180;
181181; CHECK-BE-LABEL: and_v2i64_b:
182182; CHECK-BE: @ %bb.0:
183- ; CHECK-BE-NEXT: q8, #0xff0000ff00ffff00
183+ ; CHECK-BE-NEXT: vmov.i64 q8, #0xff0000ff00ffff00
184184; CHECK-BE-NEXT: vrev64.32 q8, q8
185185; CHECK-BE-NEXT: vand q0, q0, q8
186186; CHECK-BE-NEXT: bx lr
@@ -219,6 +219,7 @@ define arm_aapcs_vfpcc <8 x i16> @vmvn_v16i8_m1() {
219219 ret <8 x i16 > <i16 65535 , i16 65534 , i16 65535 , i16 65534 , i16 65535 , i16 65534 , i16 65535 , i16 65534 >
220220}
221221
222+ ; FIXME: This is incorrect for BE
222223define arm_aapcs_vfpcc <8 x i16 > @and_v8i16_m1 (<8 x i16 > %a ) {
223224; CHECK-LE-LABEL: and_v8i16_m1:
224225; CHECK-LE: @ %bb.0:
@@ -236,6 +237,22 @@ define arm_aapcs_vfpcc <8 x i16> @and_v8i16_m1(<8 x i16> %a) {
236237}
237238
238239; FIXME: This is incorrect for BE
240+ define arm_aapcs_vfpcc <8 x i16 > @or_v8i16_1 (<8 x i16 > %a ) {
241+ ; CHECK-LE-LABEL: or_v8i16_1:
242+ ; CHECK-LE: @ %bb.0:
243+ ; CHECK-LE-NEXT: vorr.i32 q0, #0x10000
244+ ; CHECK-LE-NEXT: bx lr
245+ ;
246+ ; CHECK-BE-LABEL: or_v8i16_1:
247+ ; CHECK-BE: @ %bb.0:
248+ ; CHECK-BE-NEXT: vrev64.32 q8, q0
249+ ; CHECK-BE-NEXT: vorr.i32 q8, #0x10000
250+ ; CHECK-BE-NEXT: vrev64.32 q0, q8
251+ ; CHECK-BE-NEXT: bx lr
252+ %b = or <8 x i16 > %a , <i16 0 , i16 1 , i16 0 , i16 1 , i16 0 , i16 1 , i16 0 , i16 1 >
253+ ret <8 x i16 > %b
254+ }
255+
239256define arm_aapcs_vfpcc <8 x i16 > @xor_v8i16_m1 (<8 x i16 > %a ) {
240257; CHECK-LE-LABEL: xor_v8i16_m1:
241258; CHECK-LE: @ %bb.0:
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