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[WebAssembly] Update FP16 opcodes to match current spec. (llvm#106759)
https://github.com/WebAssembly/half-precision/blob/f267a3d54432e5723dcc13ad4530c3581a0cc4b3/proposals/half-precision/Overview.md#binary-format
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -763,7 +763,7 @@ multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst> {
763763
multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
764764
defm "" : SIMDCondition<F32x4, name, cond, baseInst>;
765765
defm "" : SIMDCondition<F64x2, name, cond, !add(baseInst, 6)>;
766-
defm "" : HalfPrecisionCondition<F16x8, name, cond, !add(baseInst, 255)>;
766+
defm "" : HalfPrecisionCondition<F16x8, name, cond, !add(baseInst, 246)>;
767767
}
768768

769769
// Equality: eq
@@ -1218,7 +1218,7 @@ multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
12181218
// Unlike F32x4 and F64x2 there's not a gap in the opcodes between "neg" and
12191219
// "sqrt" so subtract one from the offset.
12201220
defm "" : HalfPrecisionUnary<F16x8, node, name,
1221-
!add(baseInst,!if(!eq(name, "sqrt"), 80, 81))>;
1221+
!add(baseInst,!if(!eq(name, "sqrt"), 79, 80))>;
12221222
}
12231223

12241224
// Absolute value: abs
@@ -1239,10 +1239,10 @@ defm CEIL : SIMDUnary<F64x2, fceil, "ceil", 0x74>;
12391239
defm FLOOR : SIMDUnary<F64x2, ffloor, "floor", 0x75>;
12401240
defm TRUNC: SIMDUnary<F64x2, ftrunc, "trunc", 0x7a>;
12411241
defm NEAREST: SIMDUnary<F64x2, fnearbyint, "nearest", 0x94>;
1242-
defm CEIL : HalfPrecisionUnary<F16x8, fceil, "ceil", 0x13c>;
1243-
defm FLOOR : HalfPrecisionUnary<F16x8, ffloor, "floor", 0x13d>;
1244-
defm TRUNC : HalfPrecisionUnary<F16x8, ftrunc, "trunc", 0x13e>;
1245-
defm NEAREST : HalfPrecisionUnary<F16x8, fnearbyint, "nearest", 0x13f>;
1242+
defm CEIL : HalfPrecisionUnary<F16x8, fceil, "ceil", 0x133>;
1243+
defm FLOOR : HalfPrecisionUnary<F16x8, ffloor, "floor", 0x134>;
1244+
defm TRUNC : HalfPrecisionUnary<F16x8, ftrunc, "trunc", 0x135>;
1245+
defm NEAREST : HalfPrecisionUnary<F16x8, fnearbyint, "nearest", 0x136>;
12461246

12471247
// WebAssembly doesn't expose inexact exceptions, so map frint to fnearbyint.
12481248
def : Pat<(v4f32 (frint (v4f32 V128:$src))), (NEAREST_F32x4 V128:$src)>;
@@ -1261,7 +1261,7 @@ def : Pat<(v8f16 (froundeven (v8f16 V128:$src))), (NEAREST_F16x8 V128:$src)>;
12611261
multiclass SIMDBinaryFP<SDPatternOperator node, string name, bits<32> baseInst> {
12621262
defm "" : SIMDBinary<F32x4, node, name, baseInst>;
12631263
defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>;
1264-
defm "" : HalfPrecisionBinary<F16x8, node, name, !add(baseInst, 80)>;
1264+
defm "" : HalfPrecisionBinary<F16x8, node, name, !add(baseInst, 89)>;
12651265
}
12661266

12671267
// Addition: add
@@ -1362,8 +1362,8 @@ multiclass HalfPrecisionConvert<Vec vec, Vec arg, SDPatternOperator op,
13621362
// Floating point to integer with saturation: trunc_sat
13631363
defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>;
13641364
defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>;
1365-
defm "" : HalfPrecisionConvert<I16x8, F16x8, fp_to_sint, "trunc_sat_f16x8_s", 0x148>;
1366-
defm "" : HalfPrecisionConvert<I16x8, F16x8, fp_to_uint, "trunc_sat_f16x8_u", 0x149>;
1365+
defm "" : HalfPrecisionConvert<I16x8, F16x8, fp_to_sint, "trunc_sat_f16x8_s", 0x145>;
1366+
defm "" : HalfPrecisionConvert<I16x8, F16x8, fp_to_uint, "trunc_sat_f16x8_u", 0x146>;
13671367

13681368
// Support the saturating variety as well.
13691369
def trunc_s_sat32 : PatFrag<(ops node:$x), (fp_to_sint_sat $x, i32)>;
@@ -1394,8 +1394,8 @@ defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>;
13941394
defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>;
13951395
defm "" : SIMDConvert<F64x2, I32x4, convert_low_s, "convert_low_i32x4_s", 0xfe>;
13961396
defm "" : SIMDConvert<F64x2, I32x4, convert_low_u, "convert_low_i32x4_u", 0xff>;
1397-
defm "" : HalfPrecisionConvert<F16x8, I16x8, sint_to_fp, "convert_i16x8_s", 0x14a>;
1398-
defm "" : HalfPrecisionConvert<F16x8, I16x8, uint_to_fp, "convert_i16x8_u", 0x14b>;
1397+
defm "" : HalfPrecisionConvert<F16x8, I16x8, sint_to_fp, "convert_i16x8_s", 0x147>;
1398+
defm "" : HalfPrecisionConvert<F16x8, I16x8, uint_to_fp, "convert_i16x8_u", 0x148>;
13991399

14001400
// Extending operations
14011401
// TODO: refactor this to be uniform for i64x2 if the numbering is not changed.
@@ -1538,7 +1538,7 @@ multiclass SIMDMADD<Vec vec, bits<32> simdopA, bits<32> simdopS, list<Predicate>
15381538

15391539
defm "" : SIMDMADD<F32x4, 0x105, 0x106, [HasRelaxedSIMD]>;
15401540
defm "" : SIMDMADD<F64x2, 0x107, 0x108, [HasRelaxedSIMD]>;
1541-
defm "" : SIMDMADD<F16x8, 0x146, 0x147, [HasFP16]>;
1541+
defm "" : SIMDMADD<F16x8, 0x14e, 0x14f, [HasFP16]>;
15421542

15431543
//===----------------------------------------------------------------------===//
15441544
// Laneselect

‎llvm/test/MC/WebAssembly/simd-encodings.s‎

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -854,85 +854,85 @@ main:
854854
# CHECK: f16x8.replace_lane 1 # encoding: [0xfd,0xa2,0x02,0x01]
855855
f16x8.replace_lane 1
856856

857-
# CHECK: f16x8.add # encoding: [0xfd,0xb4,0x02]
857+
# CHECK: f16x8.add # encoding: [0xfd,0xbd,0x02]
858858
f16x8.add
859859

860-
# CHECK: f16x8.sub # encoding: [0xfd,0xb5,0x02]
860+
# CHECK: f16x8.sub # encoding: [0xfd,0xbe,0x02]
861861
f16x8.sub
862862

863-
# CHECK: f16x8.mul # encoding: [0xfd,0xb6,0x02]
863+
# CHECK: f16x8.mul # encoding: [0xfd,0xbf,0x02]
864864
f16x8.mul
865865

866-
# CHECK: f16x8.div # encoding: [0xfd,0xb7,0x02]
866+
# CHECK: f16x8.div # encoding: [0xfd,0xc0,0x02]
867867
f16x8.div
868868

869-
# CHECK: f16x8.min # encoding: [0xfd,0xb8,0x02]
869+
# CHECK: f16x8.min # encoding: [0xfd,0xc1,0x02]
870870
f16x8.min
871871

872-
# CHECK: f16x8.max # encoding: [0xfd,0xb9,0x02]
872+
# CHECK: f16x8.max # encoding: [0xfd,0xc2,0x02]
873873
f16x8.max
874874

875-
# CHECK: f16x8.pmin # encoding: [0xfd,0xba,0x02]
875+
# CHECK: f16x8.pmin # encoding: [0xfd,0xc3,0x02]
876876
f16x8.pmin
877877

878-
# CHECK: f16x8.pmax # encoding: [0xfd,0xbb,0x02]
878+
# CHECK: f16x8.pmax # encoding: [0xfd,0xc4,0x02]
879879
f16x8.pmax
880880

881-
# CHECK: f16x8.eq # encoding: [0xfd,0xc0,0x02]
881+
# CHECK: f16x8.eq # encoding: [0xfd,0xb7,0x02]
882882
f16x8.eq
883883

884-
# CHECK: f16x8.ne # encoding: [0xfd,0xc1,0x02]
884+
# CHECK: f16x8.ne # encoding: [0xfd,0xb8,0x02]
885885
f16x8.ne
886886

887-
# CHECK: f16x8.lt # encoding: [0xfd,0xc2,0x02]
887+
# CHECK: f16x8.lt # encoding: [0xfd,0xb9,0x02]
888888
f16x8.lt
889889

890-
# CHECK: f16x8.gt # encoding: [0xfd,0xc3,0x02]
890+
# CHECK: f16x8.gt # encoding: [0xfd,0xba,0x02]
891891
f16x8.gt
892892

893-
# CHECK: f16x8.le # encoding: [0xfd,0xc4,0x02]
893+
# CHECK: f16x8.le # encoding: [0xfd,0xbb,0x02]
894894
f16x8.le
895895

896-
# CHECK: f16x8.ge # encoding: [0xfd,0xc5,0x02]
896+
# CHECK: f16x8.ge # encoding: [0xfd,0xbc,0x02]
897897
f16x8.ge
898898

899-
# CHECK: f16x8.abs # encoding: [0xfd,0xb1,0x02]
899+
# CHECK: f16x8.abs # encoding: [0xfd,0xb0,0x02]
900900
f16x8.abs
901901

902-
# CHECK: f16x8.neg # encoding: [0xfd,0xb2,0x02]
902+
# CHECK: f16x8.neg # encoding: [0xfd,0xb1,0x02]
903903
f16x8.neg
904904

905-
# CHECK: f16x8.sqrt # encoding: [0xfd,0xb3,0x02]
905+
# CHECK: f16x8.sqrt # encoding: [0xfd,0xb2,0x02]
906906
f16x8.sqrt
907907

908-
# CHECK: f16x8.ceil # encoding: [0xfd,0xbc,0x02]
908+
# CHECK: f16x8.ceil # encoding: [0xfd,0xb3,0x02]
909909
f16x8.ceil
910910

911-
# CHECK: f16x8.floor # encoding: [0xfd,0xbd,0x02]
911+
# CHECK: f16x8.floor # encoding: [0xfd,0xb4,0x02]
912912
f16x8.floor
913913

914-
# CHECK: f16x8.trunc # encoding: [0xfd,0xbe,0x02]
914+
# CHECK: f16x8.trunc # encoding: [0xfd,0xb5,0x02]
915915
f16x8.trunc
916916

917-
# CHECK: f16x8.nearest # encoding: [0xfd,0xbf,0x02]
917+
# CHECK: f16x8.nearest # encoding: [0xfd,0xb6,0x02]
918918
f16x8.nearest
919919

920-
# CHECK: f16x8.relaxed_madd # encoding: [0xfd,0xc6,0x02]
920+
# CHECK: f16x8.relaxed_madd # encoding: [0xfd,0xce,0x02]
921921
f16x8.relaxed_madd
922922

923-
# CHECK: f16x8.relaxed_nmadd # encoding: [0xfd,0xc7,0x02]
923+
# CHECK: f16x8.relaxed_nmadd # encoding: [0xfd,0xcf,0x02]
924924
f16x8.relaxed_nmadd
925925

926-
# CHECK: i16x8.trunc_sat_f16x8_s # encoding: [0xfd,0xc8,0x02]
926+
# CHECK: i16x8.trunc_sat_f16x8_s # encoding: [0xfd,0xc5,0x02]
927927
i16x8.trunc_sat_f16x8_s
928928

929-
# CHECK: i16x8.trunc_sat_f16x8_u # encoding: [0xfd,0xc9,0x02]
929+
# CHECK: i16x8.trunc_sat_f16x8_u # encoding: [0xfd,0xc6,0x02]
930930
i16x8.trunc_sat_f16x8_u
931931

932-
# CHECK: f16x8.convert_i16x8_s # encoding: [0xfd,0xca,0x02]
932+
# CHECK: f16x8.convert_i16x8_s # encoding: [0xfd,0xc7,0x02]
933933
f16x8.convert_i16x8_s
934934

935-
# CHECK: f16x8.convert_i16x8_u # encoding: [0xfd,0xcb,0x02]
935+
# CHECK: f16x8.convert_i16x8_u # encoding: [0xfd,0xc8,0x02]
936936
f16x8.convert_i16x8_u
937937

938938
end_function

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