Shorten Verilator FPGA initial reset delay

- Makes run_simulation happy in tracing mode. There's still a bit of a
  race hiding here (slowness of trace mode means that we start talking
  to SPI DPI before the system is ready) -- but functional for now until
  we have a real fix.

Change-Id: I0c6de068fb0af379eeebf554f6b068b2a4822e46

Author: atvrager

fpga/main.cc

@@ -54,7 +54,7 @@ int main(int argc, char **argv) {
   memutil.RegisterMemoryArea("dtcm", dtcm_addr, &dtcm);
   simctrl.RegisterExtension(&memutil);
 
-  simctrl.SetInitialResetDelay(2000);
+  simctrl.SetInitialResetDelay(20);
   simctrl.SetResetDuration(10);
 
   std::cout << "Simulation of CoralNPU SoC" << std::endl