address review comments

Author: m4tx

Cargo.lock

@@ -11,8 +11,9 @@ categories = ["embedded", "no-std"]
 
 [dependencies]
 aarch64-paging = { version = "0.10", default-features = false }
-aarch64-rt = { version = "0.3", features = ["el2", "exceptions", "initial-pagetable", "psci"], default-features = false }
+aarch64-rt = { version = "0.4", features = ["el2", "exceptions", "initial-pagetable", "psci"], default-features = false }
 arm-pl011-uart = "0.4"
+arm-psci = "0.2"
 buddy_system_allocator = { version = "0.11", default-features = false, features = ["alloc", "use_spin"] }
 # TODO: replace with a crates.io version when it's released
 dtoolkit = { version = "0.1", git = "ssh://git@github.com/google/dtoolkit.git", rev = "35c8644de5fd2ff0098cfd8e493a8cffc163cf04", features = ["write"] }
@@ -23,10 +24,6 @@ safe-mmio = "0.2"
 smccc = "0.2"
 spin = { version = "0.10", features = ["lazy", "once", "spin_mutex"], default-features = false }
 
-[patch.crates-io]
-# TODO: replace with a crates.io version when this is merged: https://github.com/google/aarch64-rt/pull/31
-aarch64-rt = { git = "https://github.com/m4tx/aarch64-rt.git", rev = "a93fdb00baa88549c7e9c90a4dd1c66b164844bf" }
-
 [lints.rust]
 deprecated-safe = "warn"
 keyword-idents = "warn"

Cargo.toml

@@ -151,6 +151,7 @@ sys_reg!(spsr_el2, {
 });
 sys_reg!(elr_el2);
 sys_reg!(sp_el1);
+sys_reg!(mpidr_el1);
 
 pub(super) fn disable_mmu_and_caches() {
     invalidate_dcache();

src/arch.rs

@@ -6,69 +6,13 @@
 // option. This file may not be copied, modified, or distributed
 // except according to those terms.
 
-use core::arch::naked_asm;
-
-#[unsafe(no_mangle)]
-extern "C" fn sync_exception_current(_elr: u64, _spsr: u64) {
-    panic!("Unexpected sync_exception_current");
-}
-
-#[unsafe(no_mangle)]
-extern "C" fn irq_current(_elr: u64, _spsr: u64) {
-    panic!("Unexpected irq_current");
-}
-
-#[unsafe(no_mangle)]
-extern "C" fn fiq_current(_elr: u64, _spsr: u64) {
-    panic!("Unexpected fiq_current");
-}
-
-#[unsafe(no_mangle)]
-extern "C" fn serr_current(_elr: u64, _spsr: u64) {
-    panic!("Unexpected serr_current");
-}
-
-#[unsafe(naked)]
-#[unsafe(no_mangle)]
-#[rustfmt::skip]
-unsafe extern "C" fn sync_lower() {
-    naked_asm!(
-        // We load and store the registers from/to where aarch64 exception handler expects them:
-        // https://github.com/google/aarch64-rt/blob/047f3b0962064d334f149fe5fcd46ba57ea758ab/src/exceptions.S#L16-L65
-        "stp x29, x30, [sp, #-0x10]!",
-
-        "ldp x2, x3, [sp, #0x10]",
-        "ldp x4, x5, [sp, #0x20]",
-
-        "bl {sync_lower_impl}",
-
-        "mov x1, xzr",
-        "mov x2, xzr",
-        "mov x3, xzr",
-        "stp x0, x1, [sp, #0x10]",
-        "stp x2, x3, [sp, #0x20]",
-        "ldr x4, [sp, #8 * 22 + 16]",
-        // Return after the HVC call
-        "add x4, x4, #4",
-        "str x4, [sp, #8 * 22 + 16]",
-
-        "ldp x29, x30, [sp], #0x10",
-        "ret",
-        sync_lower_impl = sym crate::hypervisor::sync_lower_impl,
-    )
-}
-
-#[unsafe(no_mangle)]
-extern "C" fn irq_lower(_elr: u64, _spsr: u64) {
-    panic!("Unexpected irq_lower");
-}
-
-#[unsafe(no_mangle)]
-extern "C" fn fiq_lower(_elr: u64, _spsr: u64) {
-    panic!("Unexpected fiq_lower");
-}
-
-#[unsafe(no_mangle)]
-extern "C" fn serr_lower(_elr: u64, _spsr: u64) {
-    panic!("Unexpected serr_lower");
+use aarch64_rt::{ExceptionHandlers, RegisterStateRef};
+
+pub struct Exceptions;
+impl ExceptionHandlers for Exceptions {
+    extern "C" fn sync_lower(register_state: RegisterStateRef) {
+        // sync_lower exception is most likely a HVC/SMC call, which we should
+        // handle in the hypervisor.
+        crate::hypervisor::handle_sync_lower(register_state);
+    }
 }