Merge pull request #3702 from xlsynth:meheff/2026-01-18-conditional

PiperOrigin-RevId: 858774844

Author: copybara-github

xls/codegen/vast/vast.h

@@ -2280,7 +2280,7 @@ using ModuleMember =
                  VerilogFunction*,         // Function definition
                  Typedef*, Enum*, Cover*, ConcurrentAssertion*,
                  DeferredImmediateAssertion*, ModuleConditionalDirective*,
-                 ModuleSection*,
+                 ModuleSection*, Conditional*,
                  // Generate loop, can effectively generate more module members
                  // at elaboration time
                  GenerateLoop*, MacroStatement*>;

xls/codegen/vast/vast_test.cc

@@ -2884,6 +2884,86 @@ TEST_P(VastTest, NestedGenerateLoop) {
 endmodule)");
 }
 
+TEST_P(VastTest, ModuleScopeConditionalBasedOnParameterEquality) {
+  if (!UseSystemVerilog()) {
+    GTEST_SKIP();
+  }
+  VerilogFile f(GetFileType());
+  const SourceInfo si;
+  Module* m = f.AddModule("top", si);
+
+  // parameter A = 1; parameter B = 2;
+  ParameterRef* A = m->AddParameter("A", f.PlainLiteral(1, si), si);
+  ParameterRef* B = m->AddParameter("B", f.PlainLiteral(2, si), si);
+
+  // wire out;
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * out,
+                           m->AddWire("out", f.ScalarType(si), si));
+  (void)out;  // referenced via inline verilog statements below.
+
+  // Generate-style conditional at module scope based on (A == B) / (A != B).
+  Conditional* c = m->Add<Conditional>(si, f.Equals(A, B, si));
+  c->consequent()->Add<ContinuousAssignment>(si, out, f.Literal(1, 1, si));
+  StatementBlock* else_block = c->AddAlternate(/*condition=*/nullptr);
+  else_block->Add<ContinuousAssignment>(si, out, f.Literal(0, 1, si));
+
+  EXPECT_EQ(m->Emit(nullptr),
+            R"(module top;
+  parameter A = 1;
+  parameter B = 2;
+  wire out;
+  if (A == B) begin
+    assign out = 1'h1;
+  end else begin
+    assign out = 1'h0;
+  end
+endmodule)");
+}
+
+TEST_P(VastTest, GenerateLoopConditionalOnGenvarWithFallthrough) {
+  if (!UseSystemVerilog()) {
+    GTEST_SKIP();
+  }
+  VerilogFile f(GetFileType());
+  const SourceInfo si;
+  Module* m = f.AddModule("top", si);
+
+  XLS_ASSERT_OK_AND_ASSIGN(LogicRef * out,
+                           m->AddWire("out", f.BitVectorType(3, si), si));
+  (void)out;  // referenced via inline verilog statements below.
+
+  auto* loop = m->Add<GenerateLoop>(si, std::string("i"), f.PlainLiteral(0, si),
+                                    f.PlainLiteral(3, si), "g");
+  LogicRef* i = loop->genvar();
+
+  // Compare genvar to constants with else-if and fallthrough else.
+  Conditional* c =
+      loop->Add<Conditional>(si, f.Equals(i, f.PlainLiteral(0, si), si));
+  c->consequent()->Add<ContinuousAssignment>(si, f.Make<Index>(si, out, i),
+                                             f.Literal(0, 1, si));
+  StatementBlock* else_if =
+      c->AddAlternate(f.Equals(i, f.PlainLiteral(1, si), si));
+  else_if->Add<ContinuousAssignment>(si, f.Make<Index>(si, out, i),
+                                     f.Literal(1, 1, si));
+  StatementBlock* else_block = c->AddAlternate(/*condition=*/nullptr);
+  else_block->Add<ContinuousAssignment>(si, f.Make<Index>(si, out, i),
+                                        f.Make<XSentinel>(si, 1));
+
+  EXPECT_EQ(m->Emit(nullptr),
+            R"(module top;
+  wire [2:0] out;
+  for (genvar i = 0; i < 3; i = i + 1) begin : g
+    if (i == 0) begin
+      assign out[i] = 1'h0;
+    end else if (i == 1) begin
+      assign out[i] = 1'h1;
+    end else begin
+      assign out[i] = 1'dx;
+    end
+  end
+endmodule)");
+}
+
 TEST_P(VastTest, ModuleParametersPortsNoIo) {
   VerilogFile f(GetFileType());
   Module* m = f.AddModule("top", SourceInfo());

xls/public/c_api_symbols.txt

@@ -345,6 +345,7 @@ xls_vast_generate_loop_add_always_comb
 xls_vast_generate_loop_add_always_ff
 xls_vast_generate_loop_add_blank_line
 xls_vast_generate_loop_add_comment
+xls_vast_generate_loop_add_conditional
 xls_vast_generate_loop_add_continuous_assignment
 xls_vast_generate_loop_add_generate_loop
 xls_vast_generate_loop_add_inline_verilog_statement
@@ -369,6 +370,7 @@ xls_vast_statement_block_add_blocking_assignment
 xls_vast_statement_block_add_case
 xls_vast_statement_block_add_comment_text
 xls_vast_statement_block_add_conditional
+xls_vast_statement_block_add_continuous_assignment
 xls_vast_statement_block_add_inline_text
 xls_vast_statement_block_add_nonblocking_assignment
 xls_vast_verilog_file_add_blank_line
@@ -419,6 +421,7 @@ xls_vast_verilog_file_make_width_cast
 xls_vast_verilog_module_add_always_at
 xls_vast_verilog_module_add_always_comb
 xls_vast_verilog_module_add_always_ff
+xls_vast_verilog_module_add_conditional
 xls_vast_verilog_module_add_generate_loop
 xls_vast_verilog_module_add_inout
 xls_vast_verilog_module_add_input

xls/public/c_api_vast.cc

@@ -1240,6 +1240,18 @@ struct xls_vast_statement* xls_vast_statement_block_add_blocking_assignment(
   return reinterpret_cast<xls_vast_statement*>(cpp_assignment);
 }
 
+struct xls_vast_statement* xls_vast_statement_block_add_continuous_assignment(
+    struct xls_vast_statement_block* block, struct xls_vast_expression* lhs,
+    struct xls_vast_expression* rhs) {
+  auto* cpp_block = reinterpret_cast<xls::verilog::StatementBlock*>(block);
+  auto* cpp_lhs = reinterpret_cast<xls::verilog::Expression*>(lhs);
+  auto* cpp_rhs = reinterpret_cast<xls::verilog::Expression*>(rhs);
+  xls::verilog::ContinuousAssignment* cpp_assignment =
+      cpp_block->Add<xls::verilog::ContinuousAssignment>(xls::SourceInfo(),
+                                                         cpp_lhs, cpp_rhs);
+  return reinterpret_cast<xls_vast_statement*>(cpp_assignment);
+}
+
 struct xls_vast_conditional* xls_vast_statement_block_add_conditional(
     struct xls_vast_statement_block* block, struct xls_vast_expression* cond) {
   auto* cpp_block = reinterpret_cast<xls::verilog::StatementBlock*>(block);
@@ -1271,6 +1283,24 @@ struct xls_vast_statement_block* xls_vast_conditional_add_else(
   return reinterpret_cast<xls_vast_statement_block*>(block);
 }
 
+struct xls_vast_conditional* xls_vast_verilog_module_add_conditional(
+    struct xls_vast_verilog_module* m, struct xls_vast_expression* cond) {
+  auto* cpp_module = reinterpret_cast<xls::verilog::Module*>(m);
+  auto* cpp_cond = reinterpret_cast<xls::verilog::Expression*>(cond);
+  xls::verilog::Conditional* cpp_if =
+      cpp_module->Add<xls::verilog::Conditional>(xls::SourceInfo(), cpp_cond);
+  return reinterpret_cast<xls_vast_conditional*>(cpp_if);
+}
+
+struct xls_vast_conditional* xls_vast_generate_loop_add_conditional(
+    struct xls_vast_generate_loop* loop, struct xls_vast_expression* cond) {
+  auto* cpp_loop = reinterpret_cast<xls::verilog::GenerateLoop*>(loop);
+  auto* cpp_cond = reinterpret_cast<xls::verilog::Expression*>(cond);
+  xls::verilog::Conditional* cpp_if =
+      cpp_loop->Add<xls::verilog::Conditional>(xls::SourceInfo(), cpp_cond);
+  return reinterpret_cast<xls_vast_conditional*>(cpp_if);
+}
+
 struct xls_vast_case_statement* xls_vast_statement_block_add_case(
     struct xls_vast_statement_block* block,
     struct xls_vast_expression* selector) {

xls/public/c_api_vast.h

@@ -509,6 +509,12 @@ struct xls_vast_statement* xls_vast_statement_block_add_blocking_assignment(
     struct xls_vast_statement_block* block, struct xls_vast_expression* lhs,
     struct xls_vast_expression* rhs);
 
+// Adds a continuous assignment statement (assign lhs = rhs;) to a statement
+// block and returns a pointer to the created statement.
+struct xls_vast_statement* xls_vast_statement_block_add_continuous_assignment(
+    struct xls_vast_statement_block* block, struct xls_vast_expression* lhs,
+    struct xls_vast_expression* rhs);
+
 struct xls_vast_statement* xls_vast_statement_block_add_comment_text(
     struct xls_vast_statement_block* block, const char* text);
 
@@ -612,6 +618,14 @@ struct xls_vast_statement_block* xls_vast_conditional_add_else_if(
 struct xls_vast_statement_block* xls_vast_conditional_add_else(
     struct xls_vast_conditional* cond);
 
+// Adds a conditional (if) with the given condition at module scope.
+struct xls_vast_conditional* xls_vast_verilog_module_add_conditional(
+    struct xls_vast_verilog_module* m, struct xls_vast_expression* cond);
+
+// Adds a conditional (if) inside a generate loop.
+struct xls_vast_conditional* xls_vast_generate_loop_add_conditional(
+    struct xls_vast_generate_loop* loop, struct xls_vast_expression* cond);
+
 // Adds a case statement with the given selector to a statement block and
 // returns a handle to the created case statement.
 struct xls_vast_case_statement* xls_vast_statement_block_add_case(

xls/public/c_api_vast_test.cc

@@ -1047,6 +1047,203 @@ endmodule
   EXPECT_EQ(std::string_view{emitted}, kWantEmitted);
 }
 
+TEST(XlsCApiTest, VastModuleScopeConditional) {
+  const std::string_view kWantEmitted = R"(module top;
+  parameter A = 1;
+  parameter B = 2;
+  wire out;
+  if (A == B) begin
+    assign out = 1'h1;
+  end else begin
+    assign out = 1'h0;
+  end
+endmodule
+)";
+
+  xls_vast_verilog_file* f =
+      xls_vast_make_verilog_file(xls_vast_file_type_system_verilog);
+  ASSERT_NE(f, nullptr);
+  absl::Cleanup free_file([&] { xls_vast_verilog_file_free(f); });
+
+  xls_vast_verilog_module* m = xls_vast_verilog_file_add_module(f, "top");
+  ASSERT_NE(m, nullptr);
+
+  // parameter A = 1; parameter B = 2;
+  xls_vast_parameter_ref* A = xls_vast_verilog_module_add_parameter(
+      m, "A",
+      xls_vast_literal_as_expression(
+          xls_vast_verilog_file_make_plain_literal(f, 1)));
+  xls_vast_parameter_ref* B = xls_vast_verilog_module_add_parameter(
+      m, "B",
+      xls_vast_literal_as_expression(
+          xls_vast_verilog_file_make_plain_literal(f, 2)));
+  ASSERT_NE(A, nullptr);
+  ASSERT_NE(B, nullptr);
+
+  // wire out;
+  xls_vast_data_type* scalar = xls_vast_verilog_file_make_scalar_type(f);
+  ASSERT_NE(scalar, nullptr);
+  xls_vast_logic_ref* out = xls_vast_verilog_module_add_wire(m, "out", scalar);
+  ASSERT_NE(out, nullptr);
+
+  auto make_ubits_literal = [&](int64_t bit_count,
+                                uint64_t value) -> xls_vast_expression* {
+    xls_bits* bits = nullptr;
+    char* error = nullptr;
+    absl::Cleanup free_error([&] { xls_c_str_free(error); });
+    EXPECT_TRUE(xls_bits_make_ubits(bit_count, value, &error, &bits))
+        << (error ? error : "");
+    absl::Cleanup free_bits([&] { xls_bits_free(bits); });
+    xls_vast_literal* lit = nullptr;
+    EXPECT_TRUE(xls_vast_verilog_file_make_literal(
+        f, bits, xls_format_preference_hex, /*emit_bit_count=*/true, &error,
+        &lit))
+        << (error ? error : "");
+    EXPECT_NE(lit, nullptr);
+    return xls_vast_literal_as_expression(lit);
+  };
+
+  // if (A == B) ...
+  xls_vast_expression* eq = xls_vast_verilog_file_make_binary(
+      f, xls_vast_parameter_ref_as_expression(A),
+      xls_vast_parameter_ref_as_expression(B), xls_vast_operator_kind_eq);
+  ASSERT_NE(eq, nullptr);
+  xls_vast_conditional* cond = xls_vast_verilog_module_add_conditional(m, eq);
+  ASSERT_NE(cond, nullptr);
+
+  xls_vast_statement_block* then_block =
+      xls_vast_conditional_get_then_block(cond);
+  ASSERT_NE(then_block, nullptr);
+  ASSERT_NE(xls_vast_statement_block_add_continuous_assignment(
+                then_block, xls_vast_logic_ref_as_expression(out),
+                make_ubits_literal(/*bit_count=*/1, /*value=*/1)),
+            nullptr);
+
+  xls_vast_statement_block* else_block = xls_vast_conditional_add_else(cond);
+  ASSERT_NE(else_block, nullptr);
+  ASSERT_NE(xls_vast_statement_block_add_continuous_assignment(
+                else_block, xls_vast_logic_ref_as_expression(out),
+                make_ubits_literal(/*bit_count=*/1, /*value=*/0)),
+            nullptr);
+
+  char* emitted = xls_vast_verilog_file_emit(f);
+  ASSERT_NE(emitted, nullptr);
+  absl::Cleanup free_emitted([&] { xls_c_str_free(emitted); });
+  EXPECT_EQ(std::string_view{emitted}, kWantEmitted);
+}
+
+TEST(XlsCApiTest, VastGenerateLoopConditional) {
+  const std::string_view kWantEmitted = R"(module top;
+  wire [2:0] out;
+  for (genvar i = 0; i < 3; i = i + 1) begin : g
+    if (i == 0) begin
+      assign out[i] = 1'h0;
+    end else if (i == 1) begin
+      assign out[i] = 1'h1;
+    end else begin
+      assign out[i] = 'X;
+    end
+  end
+endmodule
+)";
+
+  xls_vast_verilog_file* f =
+      xls_vast_make_verilog_file(xls_vast_file_type_system_verilog);
+  ASSERT_NE(f, nullptr);
+  absl::Cleanup free_file([&] { xls_vast_verilog_file_free(f); });
+
+  xls_vast_verilog_module* m = xls_vast_verilog_file_add_module(f, "top");
+  ASSERT_NE(m, nullptr);
+
+  xls_vast_data_type* u3 =
+      xls_vast_verilog_file_make_bit_vector_type(f, 3, /*is_signed=*/false);
+  xls_vast_logic_ref* out = xls_vast_verilog_module_add_wire(m, "out", u3);
+  ASSERT_NE(out, nullptr);
+
+  xls_vast_generate_loop* loop = xls_vast_verilog_module_add_generate_loop(
+      m, "i",
+      xls_vast_literal_as_expression(
+          xls_vast_verilog_file_make_plain_literal(f, 0)),
+      xls_vast_literal_as_expression(
+          xls_vast_verilog_file_make_plain_literal(f, 3)),
+      "g");
+  ASSERT_NE(loop, nullptr);
+
+  xls_vast_logic_ref* i_lr = xls_vast_generate_loop_get_genvar(loop);
+  ASSERT_NE(i_lr, nullptr);
+
+  // Helper to form out[i] (as expression).
+  xls_vast_indexable_expression* out_idxable =
+      xls_vast_logic_ref_as_indexable_expression(out);
+  ASSERT_NE(out_idxable, nullptr);
+  xls_vast_index* out_i = xls_vast_verilog_file_make_index(
+      f, out_idxable, xls_vast_logic_ref_as_expression(i_lr));
+  ASSERT_NE(out_i, nullptr);
+  xls_vast_expression* out_i_expr = xls_vast_index_as_expression(out_i);
+  ASSERT_NE(out_i_expr, nullptr);
+
+  auto make_ubits_literal = [&](int64_t bit_count,
+                                uint64_t value) -> xls_vast_expression* {
+    xls_bits* bits = nullptr;
+    char* error = nullptr;
+    absl::Cleanup free_error([&] { xls_c_str_free(error); });
+    EXPECT_TRUE(xls_bits_make_ubits(bit_count, value, &error, &bits))
+        << (error ? error : "");
+    absl::Cleanup free_bits([&] { xls_bits_free(bits); });
+    xls_vast_literal* lit = nullptr;
+    EXPECT_TRUE(xls_vast_verilog_file_make_literal(
+        f, bits, xls_format_preference_hex, /*emit_bit_count=*/true, &error,
+        &lit))
+        << (error ? error : "");
+    EXPECT_NE(lit, nullptr);
+    return xls_vast_literal_as_expression(lit);
+  };
+
+  // if (i == 0) ...
+  xls_vast_expression* i_eq_0 = xls_vast_verilog_file_make_binary(
+      f, xls_vast_logic_ref_as_expression(i_lr),
+      xls_vast_literal_as_expression(
+          xls_vast_verilog_file_make_plain_literal(f, 0)),
+      xls_vast_operator_kind_eq);
+  ASSERT_NE(i_eq_0, nullptr);
+  xls_vast_conditional* cond =
+      xls_vast_generate_loop_add_conditional(loop, i_eq_0);
+  ASSERT_NE(cond, nullptr);
+
+  xls_vast_statement_block* then_block =
+      xls_vast_conditional_get_then_block(cond);
+  ASSERT_NE(then_block, nullptr);
+  ASSERT_NE(xls_vast_statement_block_add_continuous_assignment(
+                then_block, out_i_expr,
+                make_ubits_literal(/*bit_count=*/1, /*value=*/0)),
+            nullptr);
+
+  xls_vast_expression* i_eq_1 = xls_vast_verilog_file_make_binary(
+      f, xls_vast_logic_ref_as_expression(i_lr),
+      xls_vast_literal_as_expression(
+          xls_vast_verilog_file_make_plain_literal(f, 1)),
+      xls_vast_operator_kind_eq);
+  xls_vast_statement_block* else_if_block =
+      xls_vast_conditional_add_else_if(cond, i_eq_1);
+  ASSERT_NE(else_if_block, nullptr);
+  ASSERT_NE(xls_vast_statement_block_add_continuous_assignment(
+                else_if_block, out_i_expr,
+                make_ubits_literal(/*bit_count=*/1, /*value=*/1)),
+            nullptr);
+
+  xls_vast_statement_block* else_block = xls_vast_conditional_add_else(cond);
+  ASSERT_NE(else_block, nullptr);
+  ASSERT_NE(xls_vast_statement_block_add_continuous_assignment(
+                else_block, out_i_expr,
+                xls_vast_verilog_file_make_unsized_x_literal(f)),
+            nullptr);
+
+  char* emitted = xls_vast_verilog_file_emit(f);
+  ASSERT_NE(emitted, nullptr);
+  absl::Cleanup free_emitted([&] { xls_c_str_free(emitted); });
+  EXPECT_EQ(std::string_view{emitted}, kWantEmitted);
+}
+
 // Tests that we can assign a 128-bit output wire using a 128-bit literal
 // value.
 TEST(XlsCApiTest, ContinuousAssignmentOf128BitLiteral) {