Don't lower an unscheduled proc to a block in codegen 1.5 when pipelining is requested.

Doing so was causing xls/contrib/mlir/testdata:integration/procify.mlir.test to fail with codegen 1.5 enabled by default.

This change makes the behavior match 1.0 in this case.

PiperOrigin-RevId: 863232457

Author: richmckeever

xls/codegen_v_1_5/BUILD

@@ -142,6 +142,27 @@ cc_library(
     ],
 )
 
+cc_test(
+    name = "register_cleanup_pass_test",
+    srcs = ["register_cleanup_pass_test.cc"],
+    deps = [
+        ":block_conversion_pass",
+        ":register_cleanup_pass",
+        "//xls/common:xls_gunit_main",
+        "//xls/common/status:matchers",
+        "//xls/ir",
+        "//xls/ir:bits",
+        "//xls/ir:function_builder",
+        "//xls/ir:ir_matcher",
+        "//xls/ir:ir_test_base",
+        "//xls/ir:register",
+        "//xls/ir:source_location",
+        "//xls/passes:pass_base",
+        "@com_google_absl//absl/status:statusor",
+        "@googletest//:gtest",
+    ],
+)
+
 cc_library(
     name = "block_conversion_wrapper_pass",
     srcs = ["block_conversion_wrapper_pass.cc"],

xls/codegen_v_1_5/register_cleanup_pass.cc

@@ -127,7 +127,8 @@ absl::StatusOr<bool> RegisterCleanupPass::RemoveUnreadRegisters(
       if (user->Is<RegisterWrite>()) {
         can_receive_value_from[reg].insert(
             user->As<RegisterWrite>()->GetRegister());
-      } else if (user->Is<OutputPort>()) {
+      } else if (user->Is<OutputPort>() || user->Is<Assert>() ||
+                 user->Is<Cover>() || user->Is<Trace>()) {
         directly_read_registers.insert(reg);
       }
     }

xls/codegen_v_1_5/register_cleanup_pass_test.cc

@@ -0,0 +1,78 @@
+// Copyright 2026 The XLS Authors
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "xls/codegen_v_1_5/register_cleanup_pass.h"
+
+#include <memory>
+#include <optional>
+
+#include "gmock/gmock.h"
+#include "gtest/gtest.h"
+#include "absl/status/statusor.h"
+#include "xls/codegen_v_1_5/block_conversion_pass.h"
+#include "xls/common/status/matchers.h"
+#include "xls/ir/bits.h"
+#include "xls/ir/block.h"
+#include "xls/ir/function_builder.h"
+#include "xls/ir/ir_matcher.h"
+#include "xls/ir/ir_test_base.h"
+#include "xls/ir/node.h"
+#include "xls/ir/register.h"
+#include "xls/ir/scheduled_builder.h"
+#include "xls/ir/source_location.h"
+#include "xls/passes/pass_base.h"
+
+namespace m = xls::op_matchers;
+
+namespace xls::codegen {
+namespace {
+
+class RegisterCleanupPassTest : public IrTestBase {
+ protected:
+  absl::StatusOr<bool> Run(Package* p,
+                           const BlockConversionPassOptions& options =
+                               BlockConversionPassOptions()) {
+    PassResults results;
+    return RegisterCleanupPass().Run(p, options, &results);
+  }
+};
+
+TEST_F(RegisterCleanupPassTest, AssertConditionFromPriorStage) {
+  auto p = CreatePackage();
+  ScheduledBlockBuilder sbb(TestName(), p.get());
+  XLS_ASSERT_OK(sbb.block()->AddClockPort("clk"));
+  BValue x = sbb.InputPort("x", p->GetBitsType(32));
+
+  XLS_ASSERT_OK_AND_ASSIGN(
+      Register * reg, sbb.block()->AddRegister("x_reg", p->GetBitsType(1)));
+
+  sbb.StartStage(sbb.Literal(UBits(1, 1)), sbb.Literal(UBits(1, 1)));
+  BValue condition = sbb.UGe(x, sbb.Literal(UBits(3, 32)));
+  sbb.RegisterWrite(reg, condition);
+  sbb.EndStage(sbb.Literal(UBits(1, 1)), sbb.Literal(UBits(1, 1)));
+
+  sbb.StartStage(sbb.Literal(UBits(1, 1)), sbb.Literal(UBits(1, 1)));
+  sbb.Assert(sbb.AfterAll({}), sbb.RegisterRead(reg), "failure", std::nullopt,
+             SourceInfo{}, "assert0");
+  sbb.EndStage(sbb.Literal(UBits(1, 1)), sbb.Literal(UBits(1, 1)));
+
+  XLS_ASSERT_OK_AND_ASSIGN(ScheduledBlock * sb, sbb.Build());
+
+  XLS_ASSERT_OK(Run(p.get()).status());
+  XLS_ASSERT_OK_AND_ASSIGN(Node * assert0, sb->GetNode("assert0"));
+  EXPECT_THAT(assert0->operands()[1], Not(m::Literal()));
+}
+
+}  // namespace
+}  // namespace xls::codegen

xls/codegen_v_1_5/scheduling_pass.cc

@@ -115,7 +115,10 @@ absl::StatusOr<bool> SchedulingPass::RunInternal(
                                  return_value, Op::kIdentity));
         XLS_RETURN_IF_ERROR(new_fn->set_return_value(staged_return_value));
       }
-    } else if (old_fb->IsProc()) {
+    } else if (old_fb->IsProc() &&
+               (options.codegen_options.generate_combinational() ||
+                options.package_schedule.schedules().contains(
+                    old_fb->name()))) {
       Proc* new_proc = package->AddProc(
           std::make_unique<ScheduledProc>(old_fb->name(), package));
       new_fb = new_proc;

xls/codegen_v_1_5/scheduling_pass_test.cc

@@ -120,5 +120,46 @@ top proc __test__P_0_next(__state: bits[32], init={0}) {
   ExpectEqualToGoldenFile(output);
 }
 
+TEST_F(SchedulingPassTest, MultiProcWithOneProcScheduled) {
+  XLS_ASSERT_OK_AND_ASSIGN(
+      std::string output, RunPassAndRoundTripIrText(
+                              R"(
+package test
+
+chan test__a(bits[32], id=0, kind=streaming, ops=receive_only, flow_control=ready_valid, strictness=proven_mutually_exclusive)
+chan test__b(bits[32], id=1, kind=streaming, ops=receive_only, flow_control=ready_valid, strictness=proven_mutually_exclusive)
+chan test__result(bits[32], id=2, kind=streaming, ops=send_only, flow_control=ready_valid, strictness=proven_mutually_exclusive)
+
+proc __test2__P_0_next(__state: bits[32], init={0}) {
+  __last_state: bits[32] = state_read(state_element=__state)
+  next_value.100: () = next_value(param=__state, value=__last_state)
+}
+
+top proc __test__P_0_next(__state: bits[32], init={0}) {
+  after_all.4: token = after_all(id=4)
+  literal.3: bits[1] = literal(value=1, id=3)
+  receive.5: (token, bits[32]) = receive(after_all.4, predicate=literal.3, channel=test__a, id=5)
+  tok: token = tuple_index(receive.5, index=0, id=7)
+  receive.9: (token, bits[32]) = receive(tok, predicate=literal.3, channel=test__b, id=9)
+  a_value: bits[32] = tuple_index(receive.5, index=1, id=8)
+  b_value: bits[32] = tuple_index(receive.9, index=1, id=12)
+  umul.13: bits[32] = umul(a_value, b_value, id=13)
+  __state: bits[32] = state_read(state_element=__state, id=2)
+  tok__1: token = tuple_index(receive.9, index=0, id=11)
+  result_value: bits[32] = add(umul.13, __state, id=14)
+  __token: token = literal(value=token, id=1)
+  tuple_index.6: token = tuple_index(receive.5, index=0, id=6)
+  tuple_index.10: token = tuple_index(receive.9, index=0, id=10)
+  send.15: token = send(tok__1, result_value, predicate=literal.3, channel=test__result, id=15)
+  next_value.16: () = next_value(param=__state, value=result_value, id=16)
+}
+
+)",
+                              /*expect_change=*/true, verilog::CodegenOptions(),
+                              SchedulingOptions().pipeline_stages(2)));
+
+  ExpectEqualToGoldenFile(output);
+}
+
 }  // namespace
 }  // namespace xls::codegen

xls/codegen_v_1_5/testdata/scheduling_pass_test_MultiProcWithOneProcScheduled.ir

@@ -0,0 +1,30 @@
+package test
+
+chan test__a(bits[32], id=0, kind=streaming, ops=receive_only, flow_control=ready_valid, strictness=proven_mutually_exclusive)
+chan test__b(bits[32], id=1, kind=streaming, ops=receive_only, flow_control=ready_valid, strictness=proven_mutually_exclusive)
+chan test__result(bits[32], id=2, kind=streaming, ops=send_only, flow_control=ready_valid, strictness=proven_mutually_exclusive)
+
+proc __test2__P_0_next(__state: bits[32], init={0}) {
+  __state: bits[32] = state_read(state_element=__state, id=117)
+  next_value.100: () = next_value(param=__state, value=__state, id=100)
+}
+
+top scheduled_proc __test__P_0_next(__state: bits[32], init={0}) {
+  literal.3: bits[1] = literal(value=1, id=3)
+  stage {
+    after_all.4: token = after_all(id=4)
+    receive.5: (token, bits[32]) = receive(after_all.4, predicate=literal.3, channel=test__a, id=5)
+    tok: token = tuple_index(receive.5, index=0, id=7)
+    receive.9: (token, bits[32]) = receive(tok, predicate=literal.3, channel=test__b, id=9)
+    a_value: bits[32] = tuple_index(receive.5, index=1, id=8)
+    tok__1: token = tuple_index(receive.9, index=0, id=11)
+    b_value: bits[32] = tuple_index(receive.9, index=1, id=12)
+    umul.13: bits[32] = umul(a_value, b_value, id=13)
+  }
+  stage {
+    __state: bits[32] = state_read(state_element=__state, id=2)
+    result_value: bits[32] = add(umul.13, __state, id=14)
+    send.15: token = send(tok__1, result_value, predicate=literal.3, channel=test__result, id=15)
+    next_value.16: () = next_value(param=__state, value=result_value, id=16)
+  }
+}