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Anjian-WenRealFYang
Anjian-Wen
authored and
RealFYang
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8329887: RISC-V: C2: Support Zvbb Vector And-Not instruction
Reviewed-by: fyang, fjiang
1 parent db2dffb commit 07aad68

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‎src/hotspot/cpu/riscv/riscv_v.ad‎

Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1117,6 +1117,74 @@ instruct vxor_regL_masked(vReg dst_src, iRegL src, vRegMask_V0 v0) %{
11171117
ins_pipe(pipe_slow);
11181118
%}
11191119

1120+
// ------------------------------ Vector and not -----------------------------------
1121+
1122+
// vector and not
1123+
1124+
instruct vand_notI(vReg dst, vReg src1, vReg src2, immI_M1 m1) %{
1125+
predicate(UseZvbb);
1126+
predicate(Matcher::vector_element_basic_type(n) == T_INT ||
1127+
Matcher::vector_element_basic_type(n) == T_BYTE ||
1128+
Matcher::vector_element_basic_type(n) == T_SHORT);
1129+
match(Set dst (AndV src1 (XorV src2 (Replicate m1))));
1130+
format %{ "vand_notI $dst, $src1, $src2" %}
1131+
ins_encode %{
1132+
BasicType bt = Matcher::vector_element_basic_type(this);
1133+
__ vsetvli_helper(bt, Matcher::vector_length(this));
1134+
__ vandn_vv(as_VectorRegister($dst$$reg),
1135+
as_VectorRegister($src1$$reg),
1136+
as_VectorRegister($src2$$reg));
1137+
%}
1138+
ins_pipe(pipe_slow);
1139+
%}
1140+
1141+
instruct vand_notL(vReg dst, vReg src1, vReg src2, immL_M1 m1) %{
1142+
predicate(UseZvbb);
1143+
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
1144+
match(Set dst (AndV src1 (XorV src2 (Replicate m1))));
1145+
format %{ "vand_notL $dst, $src1, $src2" %}
1146+
ins_encode %{
1147+
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
1148+
__ vandn_vv(as_VectorRegister($dst$$reg),
1149+
as_VectorRegister($src1$$reg),
1150+
as_VectorRegister($src2$$reg));
1151+
%}
1152+
ins_pipe(pipe_slow);
1153+
%}
1154+
1155+
instruct vand_notI_masked(vReg dst_src1, vReg src2, immI_M1 m1, vRegMask_V0 v0) %{
1156+
predicate(UseZvbb);
1157+
predicate(Matcher::vector_element_basic_type(n) == T_INT ||
1158+
Matcher::vector_element_basic_type(n) == T_BYTE ||
1159+
Matcher::vector_element_basic_type(n) == T_SHORT);
1160+
match(Set dst_src1 (AndV (Binary dst_src1 (XorV src2 (Replicate m1))) v0));
1161+
format %{ "vand_notI_masked $dst_src1, $dst_src1, $src2, $v0" %}
1162+
ins_encode %{
1163+
BasicType bt = Matcher::vector_element_basic_type(this);
1164+
__ vsetvli_helper(bt, Matcher::vector_length(this));
1165+
__ vandn_vv(as_VectorRegister($dst_src1$$reg),
1166+
as_VectorRegister($dst_src1$$reg),
1167+
as_VectorRegister($src2$$reg),
1168+
Assembler::v0_t);
1169+
%}
1170+
ins_pipe(pipe_slow);
1171+
%}
1172+
1173+
instruct vand_notL_masked(vReg dst_src1, vReg src2, immL_M1 m1, vRegMask_V0 v0) %{
1174+
predicate(UseZvbb);
1175+
predicate(Matcher::vector_element_basic_type(n) == T_LONG);
1176+
match(Set dst_src1 (AndV (Binary dst_src1 (XorV src2 (Replicate m1))) v0));
1177+
format %{ "vand_notL_masked $dst_src1, $dst_src1, $src2, $v0" %}
1178+
ins_encode %{
1179+
__ vsetvli_helper(T_LONG, Matcher::vector_length(this));
1180+
__ vandn_vv(as_VectorRegister($dst_src1$$reg),
1181+
as_VectorRegister($dst_src1$$reg),
1182+
as_VectorRegister($src2$$reg),
1183+
Assembler::v0_t);
1184+
%}
1185+
ins_pipe(pipe_slow);
1186+
%}
1187+
11201188
// ------------------------------ Vector not -----------------------------------
11211189

11221190
// vector not

‎test/hotspot/jtreg/compiler/lib/ir_framework/IRNode.java‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2116,6 +2116,16 @@ public class IRNode {
21162116
machOnlyNameRegex(VAND_NOT_L, "vand_notL");
21172117
}
21182118

2119+
public static final String VAND_NOT_I_MASKED = PREFIX + "VAND_NOT_I_MASKED" + POSTFIX;
2120+
static {
2121+
machOnlyNameRegex(VAND_NOT_I_MASKED, "vand_notI_masked");
2122+
}
2123+
2124+
public static final String VAND_NOT_L_MASKED = PREFIX + "VAND_NOT_L_MASKED" + POSTFIX;
2125+
static {
2126+
machOnlyNameRegex(VAND_NOT_L_MASKED, "vand_notL_masked");
2127+
}
2128+
21192129
public static final String VECTOR_BLEND_B = VECTOR_PREFIX + "VECTOR_BLEND_B" + POSTFIX;
21202130
static {
21212131
vectorNode(VECTOR_BLEND_B, "VectorBlend", TYPE_BYTE);

‎test/hotspot/jtreg/compiler/vectorapi/AllBitsSetVectorMatchRuleTest.java‎

Lines changed: 61 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
4242
* @key randomness
4343
* @library /test/lib /
4444
* @requires vm.compiler2.enabled
45-
* @requires vm.cpu.features ~= ".*asimd.*"
45+
* @requires (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*asimd.*") | (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
4646
* @summary AArch64: [vector] Make all bits set vector sharable for match rules
4747
* @modules jdk.incubator.vector
4848
*
@@ -59,6 +59,9 @@ public class AllBitsSetVectorMatchRuleTest {
5959
private static int[] ia;
6060
private static int[] ib;
6161
private static int[] ir;
62+
private static long[] la;
63+
private static long[] lb;
64+
private static long[] lr;
6265
private static boolean[] ma;
6366
private static boolean[] mb;
6467
private static boolean[] mc;
@@ -68,6 +71,9 @@ public class AllBitsSetVectorMatchRuleTest {
6871
ia = new int[LENGTH];
6972
ib = new int[LENGTH];
7073
ir = new int[LENGTH];
74+
la = new long[LENGTH];
75+
lb = new long[LENGTH];
76+
lr = new long[LENGTH];
7177
ma = new boolean[LENGTH];
7278
mb = new boolean[LENGTH];
7379
mc = new boolean[LENGTH];
@@ -76,6 +82,8 @@ public class AllBitsSetVectorMatchRuleTest {
7682
for (int i = 0; i < LENGTH; i++) {
7783
ia[i] = RD.nextInt(25);
7884
ib[i] = RD.nextInt(25);
85+
la[i] = RD.nextLong(25);
86+
lb[i] = RD.nextLong(25);
7987
ma[i] = RD.nextBoolean();
8088
mb[i] = RD.nextBoolean();
8189
mc[i] = RD.nextBoolean();
@@ -98,8 +106,58 @@ public static void testAllBitsSetVector() {
98106

99107
@Test
100108
@Warmup(10000)
101-
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "0"})
102-
@IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIf = {"UseSVE", "> 0"})
109+
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" })
110+
public static void testVectorVAndNotL() {
111+
LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
112+
LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0);
113+
av.not().lanewise(VectorOperators.AND_NOT, bv).intoArray(lr, 0);
114+
115+
// Verify results
116+
for (int i = 0; i < L_SPECIES.length(); i++) {
117+
Asserts.assertEquals((~la[i]) & (~lb[i]), lr[i]);
118+
}
119+
}
120+
121+
@Test
122+
@Warmup(10000)
123+
@IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
124+
@IR(counts = { IRNode.VAND_NOT_I_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
125+
public static void testVectorVAndNotIMasked() {
126+
VectorMask<Integer> avm = VectorMask.fromArray(I_SPECIES, ma, 0);
127+
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
128+
IntVector bv = IntVector.fromArray(I_SPECIES, ib, 0);
129+
av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(ir, 0);
130+
131+
// Verify results
132+
for (int i = 0; i < I_SPECIES.length(); i++) {
133+
if (ma[i] == true) {
134+
Asserts.assertEquals((~ia[i]) & (~ib[i]), ir[i]);
135+
}
136+
}
137+
}
138+
139+
@Test
140+
@Warmup(10000)
141+
@IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
142+
@IR(counts = { IRNode.VAND_NOT_L_MASKED, " >= 1" }, applyIfPlatform = {"riscv64", "true"})
143+
public static void testVectorVAndNotLMasked() {
144+
VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
145+
LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
146+
LongVector bv = LongVector.fromArray(L_SPECIES, lb, 0);
147+
av.not().lanewise(VectorOperators.AND_NOT, bv, avm).intoArray(lr, 0);
148+
149+
// Verify results
150+
for (int i = 0; i < L_SPECIES.length(); i++) {
151+
if (ma[i] == true) {
152+
Asserts.assertEquals((~la[i]) & (~lb[i]), lr[i]);
153+
}
154+
}
155+
}
156+
157+
@Test
158+
@Warmup(10000)
159+
@IR(counts = { IRNode.VAND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "0"})
160+
@IR(counts = { IRNode.VMASK_AND_NOT_L, " >= 1" }, applyIfPlatform = {"aarch64", "true"}, applyIf = {"UseSVE", "> 0"})
103161
public static void testAllBitsSetMask() {
104162
VectorMask<Long> avm = VectorMask.fromArray(L_SPECIES, ma, 0);
105163
VectorMask<Long> bvm = VectorMask.fromArray(L_SPECIES, mb, 0);

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