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marwan-hallaouimarwan-hallaoui
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Merge tag 'jdk-25+30' into ola/25.0_jdk-25+30
Added tag jdk-25+30 for changeset 993215f
2 parents 9a7dbc0 + 993215f commit 7659bf1

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‎.github/workflows/main.yml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -310,7 +310,7 @@ jobs:
310310
uses: ./.github/workflows/build-windows.yml
311311
with:
312312
platform: windows-x64
313-
msvc-toolset-version: '14.43'
313+
msvc-toolset-version: '14.44'
314314
msvc-toolset-architecture: 'x86.x64'
315315
configure-arguments: ${{ github.event.inputs.configure-arguments }}
316316
make-arguments: ${{ github.event.inputs.make-arguments }}
@@ -322,7 +322,7 @@ jobs:
322322
uses: ./.github/workflows/build-windows.yml
323323
with:
324324
platform: windows-aarch64
325-
msvc-toolset-version: '14.43'
325+
msvc-toolset-version: '14.44'
326326
msvc-toolset-architecture: 'arm64'
327327
make-target: 'hotspot'
328328
extra-conf-options: '--openjdk-target=aarch64-unknown-cygwin'

‎src/demo/share/jfc/SwingSet2/resources/swingset_de.properties‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -456,13 +456,13 @@ SliderDemo.horizontal=Horizontal
456456
SliderDemo.vertical=Vertikal
457457
SliderDemo.plain=Einfach
458458
SliderDemo.a_plain_slider=Ein einfacher Schieberegler
459-
SliderDemo.majorticks=Grobteilungen
460-
SliderDemo.majorticksdescription=Ein Schieberegler mit Grobteilungsmarkierungen
461-
SliderDemo.ticks=Feinteilungen, Teilungen zum Einrasten und Labels
462-
SliderDemo.minorticks=Feinteilungen
463-
SliderDemo.minorticksdescription=Ein Schieberegler mit Grob- und Feinteilungen, mit Teilungen, in die der Schieberegler einrastet, wobei einige Teilungen mit einem sichtbaren Label versehen sind
459+
SliderDemo.majorticks=Hauptteilstriche
460+
SliderDemo.majorticksdescription=Ein Schieberegler mit Hauptteilstrichen
461+
SliderDemo.ticks=Hilfsteilstriche, zum Einrasten und Beschriften
462+
SliderDemo.minorticks=Hilfsteilstriche
463+
SliderDemo.minorticksdescription=Ein Schieberegler mit Haupt- und Hilfsteilstrichen, in die der Schieberegler einrastet, wobei einige Teilstriche mit einer sichtbaren Beschriftung versehen sind
464464
SliderDemo.disabled=Deaktiviert
465-
SliderDemo.disableddescription=Ein Schieberegler mit Grob- und Feinteilungen, der nicht aktiviert ist (kann nicht bearbeitet werden)
465+
SliderDemo.disableddescription=Ein Schieberegler mit Haupt- und Hilfsteilstrichen, der nicht aktiviert ist (kann nicht bearbeitet werden)
466466

467467
### SplitPane Demo ###
468468

‎src/hotspot/cpu/ppc/macroAssembler_ppc.cpp‎

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3928,8 +3928,10 @@ void MacroAssembler::kernel_crc32_vpmsum_aligned(Register crc, Register buf, Reg
39283928
Label L_outer_loop, L_inner_loop, L_last;
39293929

39303930
// Set DSCR pre-fetch to deepest.
3931-
load_const_optimized(t0, VM_Version::_dscr_val | 7);
3932-
mtdscr(t0);
3931+
if (VM_Version::has_mfdscr()) {
3932+
load_const_optimized(t0, VM_Version::_dscr_val | 7);
3933+
mtdscr(t0);
3934+
}
39333935

39343936
mtvrwz(VCRC, crc); // crc lives in VCRC, now
39353937

@@ -4073,8 +4075,10 @@ void MacroAssembler::kernel_crc32_vpmsum_aligned(Register crc, Register buf, Reg
40734075
// ********** Main loop end **********
40744076

40754077
// Restore DSCR pre-fetch value.
4076-
load_const_optimized(t0, VM_Version::_dscr_val);
4077-
mtdscr(t0);
4078+
if (VM_Version::has_mfdscr()) {
4079+
load_const_optimized(t0, VM_Version::_dscr_val);
4080+
mtdscr(t0);
4081+
}
40784082

40794083
// ********** Simple loop for remaining 16 byte blocks **********
40804084
{

‎src/hotspot/cpu/ppc/stubGenerator_ppc.cpp‎

Lines changed: 53 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -952,8 +952,10 @@ class StubGenerator: public StubCodeGenerator {
952952
address start_pc = __ pc();
953953
Register tmp1 = R6_ARG4;
954954
// probably copy stub would have changed value reset it.
955-
__ load_const_optimized(tmp1, VM_Version::_dscr_val);
956-
__ mtdscr(tmp1);
955+
if (VM_Version::has_mfdscr()) {
956+
__ load_const_optimized(tmp1, VM_Version::_dscr_val);
957+
__ mtdscr(tmp1);
958+
}
957959
__ li(R3_RET, 0); // return 0
958960
__ blr();
959961
return start_pc;
@@ -1070,9 +1072,10 @@ class StubGenerator: public StubCodeGenerator {
10701072
__ dcbt(R3_ARG1, 0);
10711073

10721074
// If supported set DSCR pre-fetch to deepest.
1073-
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1074-
__ mtdscr(tmp2);
1075-
1075+
if (VM_Version::has_mfdscr()) {
1076+
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1077+
__ mtdscr(tmp2);
1078+
}
10761079
__ li(tmp1, 16);
10771080

10781081
// Backbranch target aligned to 32-byte. Not 16-byte align as
@@ -1092,8 +1095,10 @@ class StubGenerator: public StubCodeGenerator {
10921095
__ bdnz(l_10); // Dec CTR and loop if not zero.
10931096

10941097
// Restore DSCR pre-fetch value.
1095-
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1096-
__ mtdscr(tmp2);
1098+
if (VM_Version::has_mfdscr()) {
1099+
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1100+
__ mtdscr(tmp2);
1101+
}
10971102

10981103
} // FasterArrayCopy
10991104

@@ -1344,8 +1349,10 @@ class StubGenerator: public StubCodeGenerator {
13441349
__ dcbt(R3_ARG1, 0);
13451350

13461351
// If supported set DSCR pre-fetch to deepest.
1347-
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1348-
__ mtdscr(tmp2);
1352+
if (VM_Version::has_mfdscr()) {
1353+
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1354+
__ mtdscr(tmp2);
1355+
}
13491356
__ li(tmp1, 16);
13501357

13511358
// Backbranch target aligned to 32-byte. It's not aligned 16-byte
@@ -1365,8 +1372,11 @@ class StubGenerator: public StubCodeGenerator {
13651372
__ bdnz(l_9); // Dec CTR and loop if not zero.
13661373

13671374
// Restore DSCR pre-fetch value.
1368-
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1369-
__ mtdscr(tmp2);
1375+
if (VM_Version::has_mfdscr()) {
1376+
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1377+
__ mtdscr(tmp2);
1378+
}
1379+
13701380
} // FasterArrayCopy
13711381
__ bind(l_6);
13721382

@@ -1527,9 +1537,10 @@ class StubGenerator: public StubCodeGenerator {
15271537
__ dcbt(R3_ARG1, 0);
15281538

15291539
// Set DSCR pre-fetch to deepest.
1530-
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1531-
__ mtdscr(tmp2);
1532-
1540+
if (VM_Version::has_mfdscr()) {
1541+
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1542+
__ mtdscr(tmp2);
1543+
}
15331544
__ li(tmp1, 16);
15341545

15351546
// Backbranch target aligned to 32-byte. Not 16-byte align as
@@ -1549,9 +1560,10 @@ class StubGenerator: public StubCodeGenerator {
15491560
__ bdnz(l_7); // Dec CTR and loop if not zero.
15501561

15511562
// Restore DSCR pre-fetch value.
1552-
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1553-
__ mtdscr(tmp2);
1554-
1563+
if (VM_Version::has_mfdscr()) {
1564+
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1565+
__ mtdscr(tmp2);
1566+
}
15551567

15561568
} // FasterArrayCopy
15571569

@@ -1672,9 +1684,10 @@ class StubGenerator: public StubCodeGenerator {
16721684
__ dcbt(R3_ARG1, 0);
16731685

16741686
// Set DSCR pre-fetch to deepest.
1675-
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1676-
__ mtdscr(tmp2);
1677-
1687+
if (VM_Version::has_mfdscr()) {
1688+
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1689+
__ mtdscr(tmp2);
1690+
}
16781691
__ li(tmp1, 16);
16791692

16801693
// Backbranch target aligned to 32-byte. Not 16-byte align as
@@ -1694,8 +1707,10 @@ class StubGenerator: public StubCodeGenerator {
16941707
__ bdnz(l_4);
16951708

16961709
// Restore DSCR pre-fetch value.
1697-
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1698-
__ mtdscr(tmp2);
1710+
if (VM_Version::has_mfdscr()) {
1711+
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1712+
__ mtdscr(tmp2);
1713+
}
16991714

17001715
__ cmpwi(CR0, R5_ARG3, 0);
17011716
__ beq(CR0, l_6);
@@ -1788,9 +1803,10 @@ class StubGenerator: public StubCodeGenerator {
17881803
__ dcbt(R3_ARG1, 0);
17891804

17901805
// Set DSCR pre-fetch to deepest.
1791-
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1792-
__ mtdscr(tmp2);
1793-
1806+
if (VM_Version::has_mfdscr()) {
1807+
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1808+
__ mtdscr(tmp2);
1809+
}
17941810
__ li(tmp1, 16);
17951811

17961812
// Backbranch target aligned to 32-byte. Not 16-byte align as
@@ -1810,8 +1826,10 @@ class StubGenerator: public StubCodeGenerator {
18101826
__ bdnz(l_5); // Dec CTR and loop if not zero.
18111827

18121828
// Restore DSCR pre-fetch value.
1813-
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1814-
__ mtdscr(tmp2);
1829+
if (VM_Version::has_mfdscr()) {
1830+
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1831+
__ mtdscr(tmp2);
1832+
}
18151833

18161834
} // FasterArrayCopy
18171835

@@ -1910,9 +1928,10 @@ class StubGenerator: public StubCodeGenerator {
19101928
__ dcbt(R3_ARG1, 0);
19111929

19121930
// Set DSCR pre-fetch to deepest.
1913-
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1914-
__ mtdscr(tmp2);
1915-
1931+
if (VM_Version::has_mfdscr()) {
1932+
__ load_const_optimized(tmp2, VM_Version::_dscr_val | 7);
1933+
__ mtdscr(tmp2);
1934+
}
19161935
__ li(tmp1, 16);
19171936

19181937
// Backbranch target aligned to 32-byte. Not 16-byte align as
@@ -1932,8 +1951,10 @@ class StubGenerator: public StubCodeGenerator {
19321951
__ bdnz(l_4);
19331952

19341953
// Restore DSCR pre-fetch value.
1935-
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1936-
__ mtdscr(tmp2);
1954+
if (VM_Version::has_mfdscr()) {
1955+
__ load_const_optimized(tmp2, VM_Version::_dscr_val);
1956+
__ mtdscr(tmp2);
1957+
}
19371958

19381959
__ cmpwi(CR0, R5_ARG3, 0);
19391960
__ beq(CR0, l_1);

‎src/hotspot/cpu/ppc/vm_version_ppc.cpp‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,9 @@ void VM_Version::initialize() {
8080
"%zu on this machine", PowerArchitecturePPC64);
8181

8282
// Power 8: Configure Data Stream Control Register.
83-
config_dscr();
83+
if (VM_Version::has_mfdscr()) {
84+
config_dscr();
85+
}
8486

8587
if (!UseSIGTRAP) {
8688
MSG(TrapBasedICMissChecks);
@@ -170,7 +172,8 @@ void VM_Version::initialize() {
170172
// Create and print feature-string.
171173
char buf[(num_features+1) * 16]; // Max 16 chars per feature.
172174
jio_snprintf(buf, sizeof(buf),
173-
"ppc64 sha aes%s%s",
175+
"ppc64 sha aes%s%s%s",
176+
(has_mfdscr() ? " mfdscr" : ""),
174177
(has_darn() ? " darn" : ""),
175178
(has_brw() ? " brw" : "")
176179
// Make sure number of %s matches num_features!
@@ -488,6 +491,7 @@ void VM_Version::determine_features() {
488491
uint32_t *code = (uint32_t *)a->pc();
489492
// Keep R3_ARG1 unmodified, it contains &field (see below).
490493
// Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
494+
a->mfdscr(R0);
491495
a->darn(R7);
492496
a->brw(R5, R6);
493497
a->blr();
@@ -524,6 +528,7 @@ void VM_Version::determine_features() {
524528

525529
// determine which instructions are legal.
526530
int feature_cntr = 0;
531+
if (code[feature_cntr++]) features |= mfdscr_m;
527532
if (code[feature_cntr++]) features |= darn_m;
528533
if (code[feature_cntr++]) features |= brw_m;
529534

‎src/hotspot/cpu/ppc/vm_version_ppc.hpp‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,14 @@
3232
class VM_Version: public Abstract_VM_Version {
3333
protected:
3434
enum Feature_Flag {
35+
mfdscr,
3536
darn,
3637
brw,
3738
num_features // last entry to count features
3839
};
3940
enum Feature_Flag_Set {
4041
unknown_m = 0,
42+
mfdscr_m = (1 << mfdscr ),
4143
darn_m = (1 << darn ),
4244
brw_m = (1 << brw ),
4345
all_features_m = (unsigned long)-1
@@ -67,8 +69,9 @@ class VM_Version: public Abstract_VM_Version {
6769

6870
static bool is_determine_features_test_running() { return _is_determine_features_test_running; }
6971
// CPU instruction support
70-
static bool has_darn() { return (_features & darn_m) != 0; }
71-
static bool has_brw() { return (_features & brw_m) != 0; }
72+
static bool has_mfdscr() { return (_features & mfdscr_m) != 0; } // Power8, but may be unavailable (QEMU)
73+
static bool has_darn() { return (_features & darn_m) != 0; }
74+
static bool has_brw() { return (_features & brw_m) != 0; }
7275

7376
// Assembler testing
7477
static void allow_all();

‎src/hotspot/cpu/x86/c2_MacroAssembler_x86.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4655,6 +4655,7 @@ static void convertF2I_slowpath(C2_MacroAssembler& masm, C2GeneralStub<Register,
46554655
__ subptr(rsp, 8);
46564656
__ movdbl(Address(rsp), src);
46574657
__ call(RuntimeAddress(target));
4658+
// APX REX2 encoding for pop(dst) increases the stub size by 1 byte.
46584659
__ pop(dst);
46594660
__ jmp(stub.continuation());
46604661
#undef __
@@ -4687,7 +4688,9 @@ void C2_MacroAssembler::convertF2I(BasicType dst_bt, BasicType src_bt, Register
46874688
}
46884689
}
46894690

4690-
auto stub = C2CodeStub::make<Register, XMMRegister, address>(dst, src, slowpath_target, 23, convertF2I_slowpath);
4691+
// Using the APX extended general purpose registers increases the instruction encoding size by 1 byte.
4692+
int max_size = 23 + (UseAPX ? 1 : 0);
4693+
auto stub = C2CodeStub::make<Register, XMMRegister, address>(dst, src, slowpath_target, max_size, convertF2I_slowpath);
46914694
jcc(Assembler::equal, stub->entry());
46924695
bind(stub->continuation());
46934696
}

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