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Commit 964d608

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author
Hamlin Li
committed
8322753: RISC-V: C2 ReverseBytesV
Reviewed-by: fyang
1 parent 2d62215 commit 964d608

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6 files changed

+41
-5
lines changed

6 files changed

+41
-5
lines changed

src/hotspot/cpu/riscv/assembler_riscv.hpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1887,8 +1887,9 @@ enum Nf {
18871887
}
18881888

18891889
// Vector Bit-manipulation used in Cryptography (Zvkb) Extension
1890-
INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010);
1891-
INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010);
1890+
INSN(vbrev_v, 0b1010111, 0b010, 0b01010, 0b010010); // reverse bits in every element
1891+
INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010); // reverse bits in every byte of element
1892+
INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010); // reverse bytes in every elememt
18921893

18931894
#undef INSN
18941895

src/hotspot/cpu/riscv/riscv_v.ad

Lines changed: 28 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -73,6 +73,7 @@ source %{
7373
return false;
7474
}
7575
break;
76+
case Op_ReverseBytesV:
7677
case Op_PopCountVL:
7778
case Op_PopCountVI:
7879
return UseZvbb;
@@ -3756,6 +3757,32 @@ instruct vsignum_reg(vReg dst, vReg zero, vReg one, vRegMask_V0 v0) %{
37563757
ins_pipe(pipe_slow);
37573758
%}
37583759

3760+
// -------------------------------- Reverse Bytes Vector Operations ------------------------
3761+
3762+
instruct vreverse_bytes_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
3763+
match(Set dst (ReverseBytesV src v0));
3764+
format %{ "vreverse_bytes_masked $dst, $src, v0" %}
3765+
ins_encode %{
3766+
BasicType bt = Matcher::vector_element_basic_type(this);
3767+
uint vlen = Matcher::vector_length(this);
3768+
__ vsetvli_helper(bt, vlen);
3769+
__ vrev8_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
3770+
%}
3771+
ins_pipe(pipe_slow);
3772+
%}
3773+
3774+
instruct vreverse_bytes(vReg dst, vReg src) %{
3775+
match(Set dst (ReverseBytesV src));
3776+
format %{ "vreverse_bytes $dst, $src" %}
3777+
ins_encode %{
3778+
BasicType bt = Matcher::vector_element_basic_type(this);
3779+
uint vlen = Matcher::vector_length(this);
3780+
__ vsetvli_helper(bt, vlen);
3781+
__ vrev8_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
3782+
%}
3783+
ins_pipe(pipe_slow);
3784+
%}
3785+
37593786
// ---------------- Convert Half Floating to Floating Vector Operations ----------------
37603787

37613788
// half precision -> single
@@ -3790,7 +3817,7 @@ instruct vconvF2HF(vReg dst, vReg src, vReg vtmp, vRegMask_V0 v0, iRegINoSp tmp)
37903817

37913818
// ------------------------------ Popcount vector ------------------------------
37923819

3793-
instruct vpopcount_mask(vReg dst, vReg src, vRegMask_V0 v0) %{
3820+
instruct vpopcount_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
37943821
match(Set dst (PopCountVI src v0));
37953822
match(Set dst (PopCountVL src v0));
37963823
ins_cost(VEC_COST);

test/hotspot/jtreg/compiler/vectorapi/VectorReverseBytesTest.java

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,8 @@
4242
* @library /test/lib /
4343
* @summary [vectorapi] REVERSE_BYTES for byte type should not emit any instructions
4444
* @requires vm.compiler2.enabled
45-
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64"
45+
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.arch == "aarch64" |
46+
* (os.arch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
4647
* @modules jdk.incubator.vector
4748
*
4849
* @run driver compiler.vectorapi.VectorReverseBytesTest

test/hotspot/jtreg/compiler/vectorization/TestReverseBytes.java

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,8 @@
2525
* @bug 8288112
2626
* @summary Auto-vectorization of ReverseBytes operations.
2727
* @requires vm.compiler2.enabled
28-
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.simpleArch == "AArch64"
28+
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") | os.simpleArch == "AArch64" |
29+
* (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
2930
* @library /test/lib /
3031
* @run driver compiler.vectorization.TestReverseBytes
3132
*/

test/hotspot/jtreg/compiler/vectorization/runner/BasicCharOpTest.java

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -227,6 +227,9 @@ public char[] vectorUnsignedShiftRight() {
227227
@Test
228228
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
229229
counts = {IRNode.REVERSE_BYTES_VS, ">0"})
230+
@IR(applyIfPlatform = {"riscv64", "true"},
231+
applyIfCPUFeature = {"zvbb", "true"},
232+
counts = {IRNode.REVERSE_BYTES_VS, ">0"})
230233
public char[] reverseBytesWithChar() {
231234
char[] res = new char[SIZE];
232235
for (int i = 0; i < SIZE; i++) {

test/hotspot/jtreg/compiler/vectorization/runner/BasicShortOpTest.java

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,9 @@ public short[] vectorUnsignedShiftRight() {
250250
@Test
251251
@IR(applyIfCPUFeatureOr = {"asimd", "true", "avx2", "true"},
252252
counts = {IRNode.REVERSE_BYTES_VS, ">0"})
253+
@IR(applyIfPlatform = {"riscv64", "true"},
254+
applyIfCPUFeature = {"zvbb", "true"},
255+
counts = {IRNode.REVERSE_BYTES_VS, ">0"})
253256
public short[] reverseBytesWithShort() {
254257
short[] res = new short[SIZE];
255258
for (int i = 0; i < SIZE; i++) {

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