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Srinivas Vamsi ParasaSandhya Viswanathan
Srinivas Vamsi Parasa
authored and
Sandhya Viswanathan
committed
8343214: Fix encoding errors in APX New Data Destination Instructions Support
Reviewed-by: jbhateja, sviswanathan
1 parent 0be7118 commit c0e6c3b

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+71
-44
lines changed

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‎src/hotspot/cpu/x86/assembler_x86.cpp‎

Lines changed: 71 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -1488,9 +1488,10 @@ void Assembler::addl(Register dst, Register src) {
14881488

14891489
void Assembler::eaddl(Register dst, Register src1, Register src2, bool no_flags) {
14901490
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1491-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
1492-
// opcode matches gcc
1493-
emit_arith(0x01, 0xC0, src1, src2);
1491+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
1492+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
1493+
(void)evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
1494+
emit_arith(0x03, 0xC0, src1, src2);
14941495
}
14951496

14961497
void Assembler::addr_nop_4() {
@@ -1728,9 +1729,10 @@ void Assembler::andl(Register dst, Register src) {
17281729

17291730
void Assembler::eandl(Register dst, Register src1, Register src2, bool no_flags) {
17301731
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1731-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
1732-
// opcode matches gcc
1733-
emit_arith(0x21, 0xC0, src1, src2);
1732+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
1733+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
1734+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
1735+
emit_arith(0x23, 0xC0, src1, src2);
17341736
}
17351737

17361738
void Assembler::andnl(Register dst, Register src1, Register src2) {
@@ -2637,7 +2639,7 @@ void Assembler::eimull(Register dst, Address src, int32_t value, bool no_flags)
26372639
InstructionMark im(this);
26382640
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
26392641
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_32bit);
2640-
evex_prefix_ndd(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
2642+
evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
26412643
if (is8bit(value)) {
26422644
emit_int8((unsigned char)0x6B);
26432645
emit_operand(dst, src, 1);
@@ -4467,7 +4469,9 @@ void Assembler::enotl(Register dst, Register src) {
44674469

44684470
void Assembler::eorw(Register dst, Register src1, Register src2, bool no_flags) {
44694471
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4470-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
4472+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
4473+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
4474+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_66, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
44714475
emit_arith(0x0B, 0xC0, src1, src2);
44724476
}
44734477

@@ -4519,9 +4523,10 @@ void Assembler::orl(Register dst, Register src) {
45194523

45204524
void Assembler::eorl(Register dst, Register src1, Register src2, bool no_flags) {
45214525
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4522-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
4523-
// opcode matches gcc
4524-
emit_arith(0x09, 0xC0, src1, src2);
4526+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
4527+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
4528+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
4529+
emit_arith(0x0B, 0xC0, src1, src2);
45254530
}
45264531

45274532
void Assembler::orl(Address dst, Register src) {
@@ -6938,7 +6943,9 @@ void Assembler::shldl(Register dst, Register src) {
69386943

69396944
void Assembler::eshldl(Register dst, Register src1, Register src2, bool no_flags) {
69406945
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6941-
int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
6946+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
6947+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
6948+
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
69426949
emit_int16(0xA5, (0xC0 | encode));
69436950
}
69446951

@@ -6949,7 +6956,9 @@ void Assembler::shldl(Register dst, Register src, int8_t imm8) {
69496956

69506957
void Assembler::eshldl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) {
69516958
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6952-
int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
6959+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
6960+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
6961+
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
69536962
emit_int24(0x24, (0xC0 | encode), imm8);
69546963
}
69556964

@@ -6960,7 +6969,9 @@ void Assembler::shrdl(Register dst, Register src) {
69606969

69616970
void Assembler::eshrdl(Register dst, Register src1, Register src2, bool no_flags) {
69626971
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6963-
int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
6972+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
6973+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
6974+
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
69646975
emit_int16(0xAD, (0xC0 | encode));
69656976
}
69666977

@@ -6971,7 +6982,9 @@ void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
69716982

69726983
void Assembler::eshrdl(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) {
69736984
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6974-
int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
6985+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
6986+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
6987+
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
69756988
emit_int24(0x2C, (0xC0 | encode), imm8);
69766989
}
69776990

@@ -6983,7 +6996,9 @@ void Assembler::shldq(Register dst, Register src, int8_t imm8) {
69836996

69846997
void Assembler::eshldq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) {
69856998
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6986-
int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
6999+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
7000+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
7001+
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
69877002
emit_int24(0x24, (0xC0 | encode), imm8);
69887003
}
69897004

@@ -6994,7 +7009,9 @@ void Assembler::shrdq(Register dst, Register src, int8_t imm8) {
69947009

69957010
void Assembler::eshrdq(Register dst, Register src1, Register src2, int8_t imm8, bool no_flags) {
69967011
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6997-
int encode = evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
7012+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
7013+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
7014+
int encode = evex_prefix_and_encode_ndd(src2->encoding(), dst->encoding(), src1->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
69987015
emit_int24(0x2C, (0xC0 | encode), imm8);
69997016
}
70007017
#endif
@@ -7155,11 +7172,12 @@ void Assembler::subl(Register dst, Register src) {
71557172
emit_arith(0x2B, 0xC0, dst, src);
71567173
}
71577174

7158-
void Assembler::esubl(Register dst, Register src2, Register src1, bool no_flags) {
7175+
void Assembler::esubl(Register dst, Register src1, Register src2, bool no_flags) {
71597176
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7160-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
7161-
// opcode matches gcc
7162-
emit_arith(0x29, 0xC0, src1, src2);
7177+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
7178+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
7179+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
7180+
emit_arith(0x2B, 0xC0, src1, src2);
71637181
}
71647182

71657183
void Assembler::subsd(XMMRegister dst, XMMRegister src) {
@@ -7485,9 +7503,10 @@ void Assembler::xorl(Register dst, Register src) {
74857503

74867504
void Assembler::exorl(Register dst, Register src1, Register src2, bool no_flags) {
74877505
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7488-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
7489-
// opcode matches gcc
7490-
emit_arith(0x31, 0xC0, src1, src2);
7506+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
7507+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
7508+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
7509+
emit_arith(0x33, 0xC0, src1, src2);
74917510
}
74927511

74937512
void Assembler::xorl(Address dst, Register src) {
@@ -7548,10 +7567,11 @@ void Assembler::xorw(Register dst, Address src) {
75487567

75497568
void Assembler::exorw(Register dst, Register src1, Address src2, bool no_flags) {
75507569
InstructionMark im(this);
7551-
emit_int8(0x66);
75527570
InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7553-
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
7554-
evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3C, &attributes, no_flags);
7571+
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_16bit);
7572+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
7573+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
7574+
evex_prefix_ndd(src2, dst->encoding(), src1->encoding(), VEX_SIMD_66, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
75557575
emit_int8(0x33);
75567576
emit_operand(src1, src2, 0);
75577577
}
@@ -15064,9 +15084,10 @@ void Assembler::addq(Register dst, Register src) {
1506415084

1506515085
void Assembler::eaddq(Register dst, Register src1, Register src2, bool no_flags) {
1506615086
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15067-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
15068-
// opcode matches gcc
15069-
emit_arith(0x01, 0xC0, src1, src2);
15087+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
15088+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
15089+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
15090+
emit_arith(0x03, 0xC0, src1, src2);
1507015091
}
1507115092

1507215093
void Assembler::adcxq(Register dst, Register src) {
@@ -15160,9 +15181,10 @@ void Assembler::andq(Register dst, Register src) {
1516015181

1516115182
void Assembler::eandq(Register dst, Register src1, Register src2, bool no_flags) {
1516215183
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15163-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
15164-
// opcode matches gcc
15165-
emit_arith(0x21, 0xC0, src1, src2);
15184+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
15185+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
15186+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
15187+
emit_arith(0x23, 0xC0, src1, src2);
1516615188
}
1516715189

1516815190
void Assembler::andq(Address dst, Register src) {
@@ -15591,7 +15613,7 @@ void Assembler::imulq(Register dst, Register src, int value) {
1559115613

1559215614
void Assembler::eimulq(Register dst, Register src, int value, bool no_flags) {
1559315615
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15594-
int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, /* src_is_gpr */ true, /* nds_is_ndd */ false, no_flags);
15616+
int encode = evex_prefix_and_encode_nf(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
1559515617
if (is8bit(value)) {
1559615618
emit_int24(0x6B, (0xC0 | encode), (value & 0xFF));
1559715619
} else {
@@ -15610,7 +15632,9 @@ void Assembler::imulq(Register dst, Address src) {
1561015632
void Assembler::eimulq(Register dst, Address src, bool no_flags) {
1561115633
InstructionMark im(this);
1561215634
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
15613-
vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes, /* nds_is_ndd */ false, no_flags);
15635+
attributes.set_address_attributes(/* tuple_type */ EVEX_NOSCALE, /* input_size_in_bits */ EVEX_64bit);
15636+
evex_prefix_nf(src, 0, dst->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
15637+
1561415638
emit_int8((unsigned char)0xAF);
1561515639
emit_operand(dst, src, 0);
1561615640
}
@@ -16055,9 +16079,10 @@ void Assembler::orq(Register dst, Register src) {
1605516079

1605616080
void Assembler::eorq(Register dst, Register src1, Register src2, bool no_flags) {
1605716081
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
16058-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
16059-
// opcode matches gcc
16060-
emit_arith(0x09, 0xC0, src1, src2);
16082+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
16083+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
16084+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
16085+
emit_arith(0x0B, 0xC0, src1, src2);
1606116086
}
1606216087

1606316088
void Assembler::popcntq(Register dst, Address src) {
@@ -16743,9 +16768,10 @@ void Assembler::subq(Register dst, Register src) {
1674316768

1674416769
void Assembler::esubq(Register dst, Register src1, Register src2, bool no_flags) {
1674516770
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
16746-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
16747-
// opcode matches gcc
16748-
emit_arith(0x29, 0xC0, src1, src2);
16771+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
16772+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
16773+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
16774+
emit_arith(0x2B, 0xC0, src1, src2);
1674916775
}
1675016776

1675116777
void Assembler::testq(Address dst, int32_t imm32) {
@@ -16807,9 +16833,10 @@ void Assembler::xorq(Register dst, Register src) {
1680716833

1680816834
void Assembler::exorq(Register dst, Register src1, Register src2, bool no_flags) {
1680916835
InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
16810-
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3C, &attributes, no_flags);
16811-
// opcode matches gcc
16812-
emit_arith(0x31, 0xC0, src1, src2);
16836+
// NDD shares its encoding bits with NDS bits for regular EVEX instruction.
16837+
// Therefore, DST is passed as the second argument to minimize changes in the leaf level routine.
16838+
(void) evex_prefix_and_encode_ndd(src1->encoding(), dst->encoding(), src2->encoding(), VEX_SIMD_NONE, /* MAP4 */VEX_OPCODE_0F_3C, &attributes, no_flags);
16839+
emit_arith(0x33, 0xC0, src1, src2);
1681316840
}
1681416841

1681516842
void Assembler::xorq(Register dst, Address src) {

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