Skip to content

Commit 96e6c84

Browse files
clamor-sclamor-s
committed
ARM: tegra: remap clock_osc_freq for all Tegra family
Enum clock_osc_freq was designed to use only with T20. This patch remaps it to use additional frequencies, added in T30+ SoC while maintaining backwards compatibility with T20. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
1 parent 1fbe0ab commit 96e6c84

File tree

9 files changed

+131
-73
lines changed

9 files changed

+131
-73
lines changed

‎arch/arm/include/asm/arch-tegra/clock.h‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -13,12 +13,13 @@ struct udevice;
1313
/* Set of oscillator frequencies supported in the internal API. */
1414
enum clock_osc_freq {
1515
/* All in MHz, so 13_0 is 13.0MHz */
16-
CLOCK_OSC_FREQ_13_0,
17-
CLOCK_OSC_FREQ_19_2,
18-
CLOCK_OSC_FREQ_12_0,
19-
CLOCK_OSC_FREQ_26_0,
16+
CLOCK_OSC_FREQ_13_0 = 0,
17+
CLOCK_OSC_FREQ_16_8,
18+
CLOCK_OSC_FREQ_19_2 = 4,
2019
CLOCK_OSC_FREQ_38_4,
20+
CLOCK_OSC_FREQ_12_0 = 8,
2121
CLOCK_OSC_FREQ_48_0,
22+
CLOCK_OSC_FREQ_26_0 = 12,
2223

2324
CLOCK_OSC_FREQ_COUNT,
2425
};

‎arch/arm/mach-tegra/clock.c‎

Lines changed: 14 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -28,16 +28,23 @@
2828
static unsigned pll_rate[CLOCK_ID_COUNT];
2929

3030
/*
31-
* The oscillator frequency is fixed to one of four set values. Based on this
31+
* The oscillator frequency is fixed to one of seven set values. Based on this
3232
* the other clocks are set up appropriately.
3333
*/
3434
static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
3535
13000000,
36+
16800000,
37+
0,
38+
0,
3639
19200000,
37-
12000000,
38-
26000000,
3940
38400000,
41+
0,
42+
0,
43+
12000000,
4044
48000000,
45+
0,
46+
0,
47+
26000000,
4148
};
4249

4350
/* return 1 if a peripheral ID is in range */
@@ -766,6 +773,7 @@ void tegra30_set_up_pllp(void)
766773
*/
767774
switch (clock_get_osc_freq()) {
768775
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
776+
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
769777
clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
770778
clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
771779
break;
@@ -776,10 +784,13 @@ void tegra30_set_up_pllp(void)
776784
break;
777785

778786
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
787+
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
779788
clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
780789
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
781790
break;
791+
782792
case CLOCK_OSC_FREQ_19_2:
793+
case CLOCK_OSC_FREQ_38_4:
783794
default:
784795
/*
785796
* These are not supported. It is too early to print a

‎arch/arm/mach-tegra/cpu.c‎

Lines changed: 56 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -55,11 +55,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
5555
*/
5656
{
5757
{ .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
58+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
59+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
60+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
5861
{ .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
62+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
63+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
64+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
5965
{ .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
66+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
67+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
68+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
6069
{ .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
61-
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
62-
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
6370
},
6471
/*
6572
* T25: 1.2 GHz
@@ -73,11 +80,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
7380
*/
7481
{
7582
{ .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
83+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
84+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
85+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
7686
{ .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
87+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
88+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
89+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
7790
{ .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
91+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
92+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
93+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
7894
{ .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
79-
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
80-
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
8195
},
8296
/*
8397
* T30: 600 MHz
@@ -91,11 +105,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
91105
*/
92106
{
93107
{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
108+
{ .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 16.8 MHz */
109+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
110+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
94111
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
112+
{ .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 38.4 MHz */
113+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
114+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
95115
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
116+
{ .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 48.0 MHz */
117+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
118+
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* N/A */
96119
{ .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
97-
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
98-
{ .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
99120
},
100121
/*
101122
* T114: 700 MHz
@@ -108,11 +129,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
108129
*/
109130
{
110131
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
132+
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
133+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
134+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
111135
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
136+
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
137+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
138+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
112139
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
140+
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
141+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
142+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
113143
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
114-
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
115-
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
116144
},
117145

118146
/*
@@ -126,11 +154,18 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
126154
*/
127155
{
128156
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
157+
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 16.8 MHz */
158+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
159+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
129160
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
161+
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 38.4 MHz */
162+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
163+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
130164
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
165+
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 48.0 MHz */
166+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
167+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
131168
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
132-
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
133-
{ .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
134169
},
135170

136171
/*
@@ -143,12 +178,19 @@ struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
143178
* PLLX_BASE m 7: 0 8
144179
*/
145180
{
146-
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
147-
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
148-
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
149-
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
181+
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz */
182+
{ .n = 108, .m = 1, .p = 1 }, /* OSC: 16.0 MHz = 702 MHz */
183+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
184+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
185+
{ .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz */
150186
{ .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
187+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
188+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
189+
{ .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz */
151190
{ .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
191+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
192+
{ .n = 0, .m = 0, .p = 0 }, /* (N/A) */
193+
{ .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz */
152194
},
153195
};
154196

‎arch/arm/mach-tegra/tegra114/clock.c‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -459,8 +459,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
459459

460460
/*
461461
* Get the oscillator frequency, from the corresponding hardware configuration
462-
* field. Note that T30/T114 support 3 new higher freqs, but we map back
463-
* to the old T20 freqs. Support for the higher oscillators is TBD.
462+
* field. Note that T30+ supports 3 new higher freqs.
464463
*/
465464
enum clock_osc_freq clock_get_osc_freq(void)
466465
{
@@ -469,12 +468,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
469468
u32 reg;
470469

471470
reg = readl(&clkrst->crc_osc_ctrl);
472-
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
473-
474-
if (reg & 1) /* one of the newer freqs */
475-
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
476-
477-
return reg >> 2; /* Map to most common (T20) freqs */
471+
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
478472
}
479473

480474
/* Returns a pointer to the clock source register for a peripheral */
@@ -674,6 +668,7 @@ void clock_early_init(void)
674668
*/
675669
switch (clock_get_osc_freq()) {
676670
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
671+
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
677672
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
678673
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
679674
break;
@@ -684,10 +679,12 @@ void clock_early_init(void)
684679
break;
685680

686681
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
682+
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
687683
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
688684
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
689685
break;
690686
case CLOCK_OSC_FREQ_19_2:
687+
case CLOCK_OSC_FREQ_38_4:
691688
default:
692689
/*
693690
* These are not supported. It is too early to print a

‎arch/arm/mach-tegra/tegra124/clock.c‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -601,8 +601,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
601601

602602
/*
603603
* Get the oscillator frequency, from the corresponding hardware configuration
604-
* field. Note that Tegra30+ support 3 new higher freqs, but we map back
605-
* to the old T20 freqs. Support for the higher oscillators is TBD.
604+
* field. Note that T30+ supports 3 new higher freqs.
606605
*/
607606
enum clock_osc_freq clock_get_osc_freq(void)
608607
{
@@ -611,12 +610,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
611610
u32 reg;
612611

613612
reg = readl(&clkrst->crc_osc_ctrl);
614-
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
615-
616-
if (reg & 1) /* one of the newer freqs */
617-
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
618-
619-
return reg >> 2; /* Map to most common (T20) freqs */
613+
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
620614
}
621615

622616
/* Returns a pointer to the clock source register for a peripheral */
@@ -854,6 +848,7 @@ void clock_early_init(void)
854848
*/
855849
switch (clock_get_osc_freq()) {
856850
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
851+
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
857852
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
858853
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
859854
break;
@@ -864,10 +859,12 @@ void clock_early_init(void)
864859
break;
865860

866861
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
862+
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
867863
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
868864
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
869865
break;
870866
case CLOCK_OSC_FREQ_19_2:
867+
case CLOCK_OSC_FREQ_38_4:
871868
default:
872869
/*
873870
* These are not supported. It is too early to print a

‎arch/arm/mach-tegra/tegra20/clock.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -399,7 +399,9 @@ enum clock_osc_freq clock_get_osc_freq(void)
399399
u32 reg;
400400

401401
reg = readl(&clkrst->crc_osc_ctrl);
402-
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
402+
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
403+
404+
return reg << 2;
403405
}
404406

405407
/* Returns a pointer to the clock source register for a peripheral */

‎arch/arm/mach-tegra/tegra210/clock.c‎

Lines changed: 4 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -672,8 +672,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
672672

673673
/*
674674
* Get the oscillator frequency, from the corresponding hardware configuration
675-
* field. Note that Tegra30+ support 3 new higher freqs, but we map back
676-
* to the old T20 freqs. Support for the higher oscillators is TBD.
675+
* field. Note that T30+ supports 3 new higher freqs.
677676
*/
678677
enum clock_osc_freq clock_get_osc_freq(void)
679678
{
@@ -682,22 +681,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
682681
u32 reg;
683682

684683
reg = readl(&clkrst->crc_osc_ctrl);
685-
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
686-
/*
687-
* 0 = 13MHz, 1 = 16.8MHz, 4 = 19.2MHz, 5 = 38.4MHz,
688-
* 8 = 12MHz, 9 = 48MHz, 12 = 26MHz
689-
*/
690-
if (reg == 5) {
691-
debug("OSC_FREQ is 38.4MHz (%d) ...\n", reg);
692-
/* Map it to the 5th CLOCK_OSC_ enum, i.e. 4 */
693-
return 4;
694-
}
695-
696-
/*
697-
* Map to most common (T20) freqs (except 38.4, handled above):
698-
* 13/16.8 = 0, 19.2 = 1, 12/48 = 2, 26 = 3
699-
*/
700-
return reg >> 2;
684+
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
701685
}
702686

703687
/* Returns a pointer to the clock source register for a peripheral */
@@ -986,6 +970,7 @@ void clock_early_init(void)
986970
*/
987971
switch (clock_get_osc_freq()) {
988972
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
973+
case CLOCK_OSC_FREQ_48_0: /* OSC is 48Mhz */
989974
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
990975
clock_set_rate(CLOCK_ID_DISPLAY, 925, 12, 0, 12);
991976
break;
@@ -996,6 +981,7 @@ void clock_early_init(void)
996981
break;
997982

998983
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
984+
case CLOCK_OSC_FREQ_16_8: /* OSC is 16.8Mhz */
999985
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
1000986
clock_set_rate(CLOCK_ID_DISPLAY, 925, 13, 0, 12);
1001987
break;

‎arch/arm/mach-tegra/tegra30/clock.c‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -439,8 +439,7 @@ struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT] = {
439439

440440
/*
441441
* Get the oscillator frequency, from the corresponding hardware configuration
442-
* field. Note that T30 supports 3 new higher freqs, but we map back
443-
* to the old T20 freqs. Support for the higher oscillators is TBD.
442+
* field. Note that T30+ supports 3 new higher freqs.
444443
*/
445444
enum clock_osc_freq clock_get_osc_freq(void)
446445
{
@@ -449,12 +448,7 @@ enum clock_osc_freq clock_get_osc_freq(void)
449448
u32 reg;
450449

451450
reg = readl(&clkrst->crc_osc_ctrl);
452-
reg = (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
453-
454-
if (reg & 1) /* one of the newer freqs */
455-
printf("Warning: OSC_FREQ is unsupported! (%d)\n", reg);
456-
457-
return reg >> 2; /* Map to most common (T20) freqs */
451+
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
458452
}
459453

460454
/* Returns a pointer to the clock source register for a peripheral */

0 commit comments

Comments
 (0)