Support new Praline configuration options in radio_* API and firmware.

Author: antoinevg

firmware/common/fpga.c

@@ -78,16 +78,16 @@ void fpga_regs_commit(fpga_driver_t* const drv)
 	}
 }
 
-void fpga_set_hw_sync_enable(fpga_driver_t* const drv, const hw_sync_mode_t hw_sync_mode)
+void fpga_set_hw_sync_enable(fpga_driver_t* const drv, const bool enable)
 {
 	fpga_reg_read(drv, FPGA_STANDARD_CTRL);
-	set_FPGA_STANDARD_CTRL_TRIGGER_EN(drv, hw_sync_mode == 1);
+	set_FPGA_STANDARD_CTRL_TRIGGER_EN(drv, enable & 0b1);
 	fpga_regs_commit(drv);
 }
 
 void fpga_set_rx_dc_block_enable(fpga_driver_t* const drv, const bool enable)
 {
-	set_FPGA_STANDARD_CTRL_DC_BLOCK(drv, enable);
+	set_FPGA_STANDARD_CTRL_DC_BLOCK(drv, enable & 0b1);
 	fpga_regs_commit(drv);
 }
 

firmware/common/fpga.h

@@ -63,7 +63,7 @@ extern void fpga_reg_write(fpga_driver_t* const drv, uint8_t r, uint8_t v);
  * provided routines for those operations. */
 extern void fpga_regs_commit(fpga_driver_t* const drv);
 
-void fpga_set_hw_sync_enable(fpga_driver_t* const drv, const hw_sync_mode_t hw_sync_mode);
+void fpga_set_hw_sync_enable(fpga_driver_t* const drv, const bool enable);
 void fpga_set_rx_dc_block_enable(fpga_driver_t* const drv, const bool enable);
 void fpga_set_rx_decimation_ratio(fpga_driver_t* const drv, const uint8_t value);
 void fpga_set_rx_quarter_shift_mode(

firmware/common/hackrf_core.c

@@ -23,6 +23,7 @@
 
 #include "hackrf_core.h"
 #include "hackrf_ui.h"
+#include "radio.h"
 #include "sgpio.h"
 #include "si5351c.h"
 #include "spi_ssp.h"
@@ -356,23 +357,23 @@ radio_t radio = {
 			.id = RADIO_CHANNEL0,
 			.config =
 				{
-					.sample_rate[RADIO_SAMPLE_RATE_CLOCKGEN] =
+					.sample_rate[RADIO_SAMPLE_RATE] =
+						{.num = 10000000, .denom = 1},
+					.filter[RADIO_FILTER_BASEBAND_LPF] = {.hz = 0},
+					.filter[RADIO_FILTER_RF_PATH] = {.mode = 0},
+					.filter[RADIO_FILTER_RX_BASEBAND_HPF] =
+						{.mode = MAX2831_RX_HPF_30_KHZ},
+					.filter[RADIO_FILTER_RX_NARROWBAND_LPF] =
 						{.hz = 0},
-					.filter[RADIO_FILTER_BASEBAND] = {.hz = 0},
-					.frequency[RADIO_FREQUENCY_RF] =
-						{
-							.hz = 0,
-							.if_hz = 0,
-							.lo_hz = 0,
-							.path = 0,
-						},
+					.filter[RADIO_FILTER_RX_DC_BLOCK] = {.hz = 0},
+					.frequency[RADIO_FREQUENCY] = {.hz = 0},
 					.gain[RADIO_GAIN_RF_AMP] = {.enable = 0},
 					.gain[RADIO_GAIN_RX_LNA] = {.db = 0},
 					.gain[RADIO_GAIN_RX_VGA] = {.db = 0},
 					.gain[RADIO_GAIN_TX_VGA] = {.db = 0},
 					.antenna[RADIO_ANTENNA_BIAS_TEE] =
 						{.enable = false},
-					.mode = TRANSCEIVER_MODE_OFF,
+					.mode = RADIO_MODE_OFF,
 					.clock[RADIO_CLOCK_CLKIN] = {.enable = false},
 					.clock[RADIO_CLOCK_CLKOUT] = {.enable = false},
 					.trigger_mode = HW_SYNC_MODE_OFF,

firmware/common/hackrf_core.h

@@ -40,7 +40,6 @@ extern "C" {
 #include "mixer.h"
 #include "w25q80bv.h"
 #include "sgpio.h"
-#include "radio.h"
 #include "rf_path.h"
 #include "cpld_jtag.h"
 #include "ice40_spi.h"
@@ -389,6 +388,26 @@ extern "C" {
 #define SCU_H1R9_NO_VAA_EN  (P6_10) /* GPIO3[6] on P6_10 */
 #define SCU_H1R9_HW_SYNC_EN (P2_5)  /* GPIO5[5] on P2_5 */
 
+typedef enum {
+	TRANSCEIVER_MODE_OFF = 0,
+	TRANSCEIVER_MODE_RX = 1,
+	TRANSCEIVER_MODE_TX = 2,
+	TRANSCEIVER_MODE_SS = 3,
+	TRANSCEIVER_MODE_CPLD_UPDATE = 4,
+	TRANSCEIVER_MODE_RX_SWEEP = 5,
+} transceiver_mode_t;
+
+typedef enum {
+	HW_SYNC_MODE_OFF = 0,
+	HW_SYNC_MODE_ON = 1,
+} hw_sync_mode_t;
+
+typedef enum {
+	CLOCK_SOURCE_HACKRF = 0,
+	CLOCK_SOURCE_EXTERNAL = 1,
+	CLOCK_SOURCE_PORTAPACK = 2,
+} clock_source_t;
+
 void delay(uint32_t duration);
 void delay_us_at_mhz(uint32_t us, uint32_t mhz);
 
@@ -410,7 +429,6 @@ extern max5864_driver_t max5864;
 extern mixer_driver_t mixer;
 extern w25q80bv_driver_t spi_flash;
 extern sgpio_config_t sgpio_config;
-extern radio_t radio;
 extern rf_path_t rf_path;
 extern jtag_t jtag_cpld;
 extern i2c_bus_t i2c0;

firmware/common/max2831.c

@@ -254,19 +254,9 @@ void max2831_set_frequency(max2831_driver_t* const drv, uint32_t freq)
 	max2831_regs_commit(drv);
 }
 
-typedef struct {
-	uint32_t bandwidth_hz;
-	uint8_t ft;
-} max2831_ft_t;
-
-typedef struct {
-	uint8_t percent;
-	uint8_t ft_fine;
-} max2831_ft_fine_t;
-
 // clang-format off
 /* measured -0.5 dB complex baseband bandwidth for each register setting */
-static const max2831_ft_t max2831_rx_ft[] = {
+static const max2831_ft_t _max2831_rx_ft[] = {
 	{ 11600000, MAX2831_RX_LPF_7_5M },
 	{ 15100000, MAX2831_RX_LPF_8_5M },
 	{ 22600000, MAX2831_RX_LPF_15M },
@@ -283,7 +273,7 @@ static const max2831_ft_fine_t max2831_rx_ft_fine[] = {
 	{   0, 0 },
 };
 
-static const max2831_ft_t max2831_tx_ft[] = {
+static const max2831_ft_t _max2831_tx_ft[] = {
 	{ 16000000, MAX2831_TX_LPF_8M },
 	{ 22000000, MAX2831_TX_LPF_11M },
 	{ 33000000, MAX2831_TX_LPF_16_5M },
@@ -302,6 +292,9 @@ static const max2831_ft_fine_t max2831_tx_ft_fine[] = {
 };
 //clang-format on
 
+// dirty hack is dirty
+const max2831_ft_t* max2831_rx_ft = _max2831_rx_ft;
+const max2831_ft_t* max2831_tx_ft = _max2831_tx_ft;
 
 uint32_t max2831_set_lpf_bandwidth(max2831_driver_t* const drv, const uint32_t bandwidth_hz) {
 	const max2831_ft_t* coarse;

firmware/common/max2831.h

@@ -65,6 +65,20 @@ struct max2831_driver_t {
 	uint32_t desired_lpf_bw;
 };
 
+typedef struct {
+	uint32_t bandwidth_hz;
+	uint8_t ft;
+} max2831_ft_t;
+
+typedef struct {
+	uint8_t percent;
+	uint8_t ft_fine;
+} max2831_ft_fine_t;
+
+// dirty hack is dirty
+extern const max2831_ft_t* max2831_rx_ft;
+extern const max2831_ft_t* max2831_tx_ft;
+
 /* Initialize chip. */
 extern void max2831_setup(max2831_driver_t* const drv);
 

firmware/common/max2837.c

@@ -284,13 +284,8 @@ void max2837_set_frequency(max2837_driver_t* const drv, uint32_t freq)
 	max2837_regs_commit(drv);
 }
 
-typedef struct {
-	uint32_t bandwidth_hz;
-	uint32_t ft;
-} max2837_ft_t;
-
 // clang-format off
-static const max2837_ft_t max2837_ft[] = {
+static const max2837_ft_t _max2837_ft[] = {
 	{  1750000, MAX2837_FT_1_75M },
 	{  2500000, MAX2837_FT_2_5M },
 	{  3500000, MAX2837_FT_3_5M },
@@ -311,6 +306,9 @@ static const max2837_ft_t max2837_ft[] = {
 };
 //clang-format on
 
+// dirty hack is dirty
+const max2837_ft_t* max2837_ft = _max2837_ft;
+
 uint32_t max2837_set_lpf_bandwidth(max2837_driver_t* const drv, const uint32_t bandwidth_hz) {
 	const max2837_ft_t* p = max2837_ft;
 	while( p->bandwidth_hz != 0 ) {

firmware/common/max2837.h

@@ -56,6 +56,14 @@ struct max2837_driver_t {
 	uint32_t regs_dirty;
 };
 
+typedef struct {
+	uint32_t bandwidth_hz;
+	uint32_t ft;
+} max2837_ft_t;
+
+// dirty hack is dirty
+extern const max2837_ft_t* max2837_ft;
+
 /* Initialize chip. */
 extern void max2837_setup(max2837_driver_t* const drv);