Hat Redesign for improved 100MHz+ performance

[Jaystonian]

I redesigned this without looking at the existing hat made for this project, and had some other things in mind for repurposing GPIO0 to GPIO3 but can still be used for chaining multiple boards with a twisted pair if disconnected from the 74ALVC245 by solderjumpers. I wasn't fully aware how you were using your hat so I will redesign to link GPIO0 and GPIO1 more easily. Intended for 0.8mm PCB thickness with a pure ground plane on bottom, and top ground filled. This design should perform better than the existing hat for 100MHz and higher operation. Focused on clean power, reduced ground bounce, mitigated ringing on probe leads. Should get good clean edges at 100MHz. You can get five of these from jlcpcb for $2 (remember 0.8mm thickness) and give it a test. I can redesign for integration into your project space at your discretion with feedback.

https://github.com/Jaystonian/ClearLogicAnalyzer

[gusmanb]

You got some things very wrong...

First of all, the TXU is not bidirectional, is the unidirectional, high-speed, schmitt-triggered version of the family, you are mixing it with the TXB. It is intended for push-pull up to 200Mhz from a range of 1.1v up to 5.5v. Check the datasheet.

Next, the 74ALVC245 only supports up to 3.6v, that's less than what the Pico 2 itself supports, right now the GPIOs of the pico have been certified to 5v (but only if the IOVDD is supplied).

Also, your design has not matched length traces, so it will perform worse at 100+Mhz.

Finally, you cannot repurpose GPIO0/1, else the complex trigger will stop working, this is the intercom mechanism between the PIO machines.

Maybe you should reconsider the design...

[Jaystonian]

Okay I misunderstood. So if I get rid of 13 channels, then it would work for 31 channels? I'm not sure what I would use GPIO output for, and I want to keep it "RF clean" so no radio signals. Also requires to remain a 4-layer PCB so the "In1" ground plane is as close as possible to the signal traces.

[gusmanb]

I was talking about my new design when I named the RP2350B, but I'm going to use it because I want to be able also to generate signals and add WiFi using an external ESP-01s module.

I made a mistake when I stated that you would have 30 channels, the RP2350A is only 30 GPIOs so you will have 28 channels, and what I recommended is to place two RP2350A in a single board with a USB hub, you will get 56 channels and a single USB cable to deal with, connecting GPIO0/1 of both devices together they will work in sync as a single device (in the app you will detect two devices and then one will work as master) and then that's why I also commented to use a single clock for both of these RP2350A, I would not send a clock through a connector for different boards to avoid problems. Doing this you could still stack two boards and have 112 channels, which is a massive quantity.

Of course if you really want to add the SPI memory then you will have one channel less per CPU, GPIO 19 (as is the only that you will be able to use to avoid breaking the complex trigger).

Anyways, if your use case is for high-speed, the PSRAM memory makes no sense, with 8 channels per device as I said I expect around 40Msps at best, so keep that in mind, do not try to overcomplicate it, you have a specific use case, I implement all of this because my use case is the "general case", an all-in-one that must perform well in every scenario.

[Jaystonian]

1. The APS6404L-3SQR-SN is QuadSPI PSRAM capable of 133MHz. The data bus width is 4 bits, because its Quad SPI. I'm not sure where you're getting 8 channels, only one channel (GPIO8) is required for enabling its /CE line. The other QSPI signals are shared with the Flash NOR QSPI.

2. So I should move the RAM enable to GPIO19 instead of using GPIO8? I had asked previously which to use to be compatible with firmware and never got a direct answer.

3. I'm confused by your mistake, as I would prefer to use a RP2350B, not a RP2350A. Are you saying in either case I'm limited to 32 GPIO, so 31 available channels for the B, and 28 channels for the A?

4. The 12MHz clock driven an inch by a 74LVC04 through a header connector is fine, I've done this before.

[gusmanb]

1. The APS6404L-3SQR-SN is QuadSPI PSRAM capable of 133MHz. The data bus width is 4 bits, because its Quad SPI. I'm not sure where you're getting 8 channels, only one channel (GPIO8) is required for enabling its /CE line. The other QSPI signals are shared with the Flash NOR QSPI.

You should really read the content of the messages, not read them diagonally...
with 8 channels per device as I said I expect around 40Msps at best 8 channels = 1 byte, so 40Mbytes/s at maximum. First you will not reach the 133Mhz, because how the memory gets configured usually it will get around 100Mhz, and then, you're ignoring completelly the transaction bytes, so 40Msps is the best you will get when capturing 8 channels, 20Msps with 16 channels and 10Msps with 32 channels.

2. So I should move the RAM enable to GPIO19 instead of using GPIO8?  I had asked previously which to use to be compatible with firmware and never got a direct answer.

You got it: The pin, my idea is to make it also configurable in the device definition, as there will be devices with and without RAM, using the RP2350A and B, it will be needed. While the selected pin is one which can be set to the QMI CS1n function it should be enough.

Use whichever you want, but the complex trigger requires 16 consecutive channels, so with the RP2350A the only one that would not break this will be GPIO19.

3. I'm confused by your mistake, as I would prefer to use a RP2350B, not a RP2350A.  Are you saying in either case I'm limited to 32 GPIO, so 31 available channels for the B, and 28 channels for the A?

Yes, you are limited to 32 channels as a PIO unit can only use 32 channels. Do you know how the RP2350 works or are you blindly doing modifications?

[Jaystonian]

Look I'm just trying to help while satisfying my own needs, because your project as it stands won't work for me whatsoever. The biggest problems were your selection of translators and your PCB design. There's something like 30 rules to follow and if you're only going to follow 5 or 6 then you may as well not follow any at all.