3030#include "esp_bt.h"
3131#include "freertos/semphr.h"
3232#include "esp_compiler.h"
33+ #include "esp_ipc.h"
3334
3435#define NIMBLE_VHCI_TIMEOUT_MS 2000
3536
@@ -78,21 +79,29 @@ void ble_hci_trans_cfg_hs(ble_hci_trans_rx_cmd_fn *cmd_cb,
7879 ble_hci_rx_acl_hs_arg = acl_arg ;
7980}
8081
82+ void ble_hci_trans_hs_cmd_tx_on_core_0 (void * arg )
83+ {
84+ uint8_t * cmd = arg ;
85+ uint16_t len = BLE_HCI_CMD_HDR_LEN + cmd [3 ] + 1 ;
86+ esp_vhci_host_send_packet (cmd , len );
87+ }
8188
8289int ble_hci_trans_hs_cmd_tx (uint8_t * cmd )
8390{
84- uint16_t len ;
8591 uint8_t rc = 0 ;
8692
8793 assert (cmd != NULL );
8894 * cmd = BLE_HCI_UART_H4_CMD ;
89- len = BLE_HCI_CMD_HDR_LEN + cmd [3 ] + 1 ;
9095 if (!esp_vhci_host_check_send_available ()) {
9196 ESP_LOGD (TAG , "Controller not ready to receive packets" );
9297 }
9398
9499 if (xSemaphoreTake (vhci_send_sem , NIMBLE_VHCI_TIMEOUT_MS / portTICK_PERIOD_MS ) == pdTRUE ) {
95- esp_vhci_host_send_packet (cmd , len );
100+ if (xPortGetCoreID () != 0 ) {
101+ esp_ipc_call_blocking (0 , ble_hci_trans_hs_cmd_tx_on_core_0 , cmd );
102+ } else {
103+ ble_hci_trans_hs_cmd_tx_on_core_0 (cmd );
104+ }
96105 } else {
97106 rc = BLE_HS_ETIMEOUT_HCI ;
98107 }
@@ -111,27 +120,37 @@ int ble_hci_trans_ll_evt_tx(uint8_t *hci_ev)
111120 return rc ;
112121}
113122
123+ void ble_hci_trans_hs_acl_tx_on_core_0 (void * arg )
124+ {
125+ uint8_t data [MYNEWT_VAL (BLE_ACL_BUF_SIZE ) + 1 ];
126+ struct os_mbuf * om = arg ;
127+ uint16_t len = 1 + OS_MBUF_PKTLEN (om );
128+
129+ data [0 ] = BLE_HCI_UART_H4_ACL ;
130+ os_mbuf_copydata (om , 0 , OS_MBUF_PKTLEN (om ), & data [1 ]);
131+
132+ esp_vhci_host_send_packet (data , len );
133+ }
134+
114135int ble_hci_trans_hs_acl_tx (struct os_mbuf * om )
115136{
116- uint16_t len = 0 ;
117- uint8_t data [MYNEWT_VAL (BLE_ACL_BUF_SIZE ) + 1 ], rc = 0 ;
137+ uint8_t rc = 0 ;
118138 /* If this packet is zero length, just free it */
119139 if (OS_MBUF_PKTLEN (om ) == 0 ) {
120140 os_mbuf_free_chain (om );
121141 return 0 ;
122142 }
123- data [0 ] = BLE_HCI_UART_H4_ACL ;
124- len ++ ;
125143
126144 if (!esp_vhci_host_check_send_available ()) {
127145 ESP_LOGD (TAG , "Controller not ready to receive packets" );
128146 }
129147
130- os_mbuf_copydata (om , 0 , OS_MBUF_PKTLEN (om ), & data [1 ]);
131- len += OS_MBUF_PKTLEN (om );
132-
133148 if (xSemaphoreTake (vhci_send_sem , NIMBLE_VHCI_TIMEOUT_MS / portTICK_PERIOD_MS ) == pdTRUE ) {
134- esp_vhci_host_send_packet (data , len );
149+ if (xPortGetCoreID () != 0 ) {
150+ esp_ipc_call_blocking (0 , ble_hci_trans_hs_acl_tx_on_core_0 , om );
151+ } else {
152+ ble_hci_trans_hs_acl_tx_on_core_0 (om );
153+ }
135154 } else {
136155 rc = BLE_HS_ETIMEOUT_HCI ;
137156 }
0 commit comments