-
Notifications
You must be signed in to change notification settings - Fork 1.1k
Expand file tree
/
Copy pathCodeGen_D3D12Compute_Dev.cpp
More file actions
1378 lines (1215 loc) · 50.2 KB
/
CodeGen_D3D12Compute_Dev.cpp
File metadata and controls
1378 lines (1215 loc) · 50.2 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
#include <algorithm>
#include <iomanip>
#include <sstream>
#include <utility>
#include "CanonicalizeGPUVars.h"
#include "CodeGen_D3D12Compute_Dev.h"
#include "CodeGen_GPU_Dev.h"
#include "CodeGen_Internal.h"
#include "Debug.h"
#include "DeviceArgument.h"
#include "IRMutator.h"
#include "IROperator.h"
#include "Simplify.h"
#define DEBUG_TYPES (0)
namespace Halide {
namespace Internal {
using std::ostringstream;
using std::sort;
using std::string;
using std::vector;
namespace {
ostringstream nil;
class CodeGen_D3D12Compute_Dev : public CodeGen_GPU_Dev {
public:
CodeGen_D3D12Compute_Dev(const Target &target);
/** Compile a GPU kernel into the module. This may be called many times
* with different kernels, which will all be accumulated into a single
* source module shared by a given Halide pipeline. */
void add_kernel(Stmt stmt,
const std::string &name,
const std::vector<DeviceArgument> &args) override;
/** (Re)initialize the GPU kernel module. This is separate from compile,
* since a GPU device module will often have many kernels compiled into it
* for a single pipeline. */
void init_module() override;
std::vector<char> compile_to_src() override;
std::string get_current_kernel_name() override;
void dump() override;
std::string print_gpu_name(const std::string &name) override;
std::string api_unique_name() override {
return "d3d12compute";
}
bool kernel_run_takes_types() const override {
return true;
}
protected:
friend struct StoragePackUnpack;
class CodeGen_D3D12Compute_C : public CodeGen_GPU_C {
public:
CodeGen_D3D12Compute_C(std::ostream &s, const Target &t)
: CodeGen_GPU_C(s, t) {
integer_suffix_style = IntegerSuffixStyle::HLSL;
#define alias(x, y) \
extern_function_name_map[x "_f16"] = y; \
extern_function_name_map[x "_f32"] = y; \
extern_function_name_map[x "_f64"] = y
alias("sqrt", "sqrt");
alias("sin", "sin");
alias("cos", "cos");
alias("exp", "exp");
alias("log", "log");
alias("abs", "abs");
alias("floor", "floor");
alias("ceil", "ceil");
alias("trunc", "trunc");
alias("pow", "pow");
alias("asin", "asin");
alias("acos", "acos");
alias("tan", "tan");
alias("atan", "atan");
alias("atan2", "atan2");
alias("sinh", "sinh");
alias("asinh", "asinh");
alias("cosh", "cosh");
alias("acosh", "acosh");
alias("tanh", "tanh");
alias("atanh", "atanh");
alias("is_nan", "isnan");
alias("is_inf", "isinf");
alias("is_finite", "isfinite");
alias("fast_inverse", "rcp");
alias("fast_inverse_sqrt", "rsqrt");
#undef alias
}
void add_kernel(Stmt stmt,
const std::string &name,
const std::vector<DeviceArgument> &args);
protected:
friend struct StoragePackUnpack;
std::string print_type(Type type, AppendSpaceIfNeeded space_option = DoNotAppendSpace) override;
std::string print_storage_type(Type type);
std::string print_type_maybe_storage(Type type, bool storage, AppendSpaceIfNeeded space);
std::string print_reinterpret(Type type, const Expr &e) override;
std::string print_vanilla_cast(Type type, const std::string &value_expr);
std::string print_reinforced_cast(Type type, const std::string &value_expr);
std::string print_cast(Type target_type, Type source_type, const std::string &value_expr);
std::string print_reinterpret_cast(Type type, const std::string &value_expr);
std::string print_assignment(Type t, const std::string &rhs) override;
using CodeGen_GPU_C::visit;
void visit(const Evaluate *op) override;
void visit(const Min *) override;
void visit(const Max *) override;
void visit(const Div *) override;
void visit(const Mod *) override;
void visit(const For *) override;
void visit(const Ramp *op) override;
void visit(const Broadcast *op) override;
void visit(const Call *op) override;
void visit(const Load *op) override;
void visit(const Store *op) override;
void visit(const Select *op) override;
void visit(const Allocate *op) override;
void visit(const Free *op) override;
void visit(const Cast *op) override;
void visit(const Atomic *op) override;
void visit(const FloatImm *op) override;
Scope<> groupshared_allocations;
};
std::ostringstream src_stream;
std::string cur_kernel_name;
CodeGen_D3D12Compute_C d3d12compute_c;
};
CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_Dev(const Target &t)
: d3d12compute_c(src_stream, t) {
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_type_maybe_storage(Type type, bool storage, AppendSpaceIfNeeded space) {
ostringstream oss;
// Storage uses packed vector types.
if (storage && type.lanes() != 1) {
// NOTE(marcos): HLSL has 'packoffset' but it only applies to constant
// buffer fields (constant registers (c)); because constant arguments
// are always converted to 32bit values by the runtime prior to kernel
// dispatch, there is no need to complicate things with packoffset.
}
if (type.is_float()) {
switch (type.bits()) {
case 16:
// 16-bit floating point value. This data type is provided only for language compatibility.
// Direct3D 10 shader targets map all half data types to float data types.
// A half data type cannot be used on a uniform global variable (use the /Gec flag if this functionality is desired).
oss << "half";
break;
case 32:
oss << "float";
break;
case 64:
// "64-bit floating point value. You cannot use double precision values as inputs and outputs for a stream.
// To pass double precision values between shaders, declare each double as a pair of uint data types.
// Then, use the asdouble function to pack each double into the pair of uints and the asuint function to
// unpack the pair of uints back into the double."
user_error << "HLSL (SM 5.1) does not have transparent support for 'double' types.\n";
oss << "double";
break;
default:
user_error << "Can't represent a float with this many bits in HLSL (SM 5.1): " << type << "\n";
}
} else {
switch (type.bits()) {
case 1:
oss << "bool";
break;
case 8:
case 16:
case 32:
if (type.is_uint()) {
oss << "u";
}
oss << "int";
#if DEBUG_TYPES
oss << type.bits();
#endif
break;
case 64:
user_error << "HLSL (SM 5.1) does not support 64-bit integers.\n";
break;
default:
user_error << "Can't represent an integer with this many bits in HLSL (SM 5.1): " << type << "\n";
}
}
switch (type.lanes()) {
case 1:
break;
case 2:
case 3:
case 4:
#if DEBUG_TYPES
oss << "_(";
#endif
oss << type.lanes();
#if DEBUG_TYPES
oss << ")";
#endif
break;
case 8:
case 16:
// TODO(marcos): are there 8-wide and 16-wide types in HLSL?
// (CodeGen_GLSLBase seems to happily generate invalid vector types)
default:
user_error << "Unsupported vector width in HLSL (SM 5.1): " << type << "\n";
}
if (space == AppendSpace) {
oss << " ";
}
return oss.str();
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_type(Type type, AppendSpaceIfNeeded space) {
return print_type_maybe_storage(type, false, space);
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_storage_type(Type type) {
return print_type_maybe_storage(type, true, DoNotAppendSpace);
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_reinterpret(Type type, const Expr &e) {
if (type == e.type()) {
return print_expr(e);
} else {
return print_reinterpret_cast(type, print_expr(e));
}
}
namespace {
string simt_intrinsic(const string &name) {
if (ends_with(name, gpu_thread_name(0))) {
return "tid_in_tgroup.x";
} else if (ends_with(name, gpu_thread_name(1))) {
return "tid_in_tgroup.y";
} else if (ends_with(name, gpu_thread_name(2))) {
return "tid_in_tgroup.z";
} else if (ends_with(name, gpu_block_name(0))) {
return "tgroup_index.x";
} else if (ends_with(name, gpu_block_name(1))) {
return "tgroup_index.y";
} else if (ends_with(name, gpu_block_name(2))) {
return "tgroup_index.z";
}
internal_error << "simt_intrinsic called on bad variable name: " << name << "\n";
return "";
}
} // namespace
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Evaluate *op) {
if (is_const(op->value)) {
return;
}
print_expr(op->value);
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Max *op) {
print_expr(Call::make(op->type, "max", {op->a, op->b}, Call::Extern));
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Min *op) {
print_expr(Call::make(op->type, "min", {op->a, op->b}, Call::Extern));
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Div *op) {
if (auto bits = is_const_power_of_two_integer(op->b)) {
ostringstream oss;
oss << print_expr(op->a) << " >> " << *bits;
print_assignment(op->type, oss.str());
} else if (op->type.is_int()) {
print_expr(lower_euclidean_div(op->a, op->b));
} else {
visit_binop(op->type, op->a, op->b, "/");
}
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Mod *op) {
if (auto bits = is_const_power_of_two_integer(op->b)) {
ostringstream oss;
oss << print_expr(op->a) << " & " << (((uint64_t)1 << *bits) - 1);
print_assignment(op->type, oss.str());
} else if (op->type.is_int()) {
print_expr(lower_euclidean_mod(op->a, op->b));
} else {
visit_binop(op->type, op->a, op->b, "%");
}
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const For *loop) {
user_assert(loop->for_type != ForType::GPULane)
<< "The D3D12Compute backend does not support the gpu_lanes() scheduling directive.";
if (!is_gpu(loop->for_type)) {
CodeGen_GPU_C::visit(loop);
return;
}
internal_assert(is_const_zero(loop->min));
stream << get_indent() << print_type(Int(32)) << " " << print_name(loop->name)
<< " = " << simt_intrinsic(loop->name) << ";\n";
loop->body.accept(this);
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Ramp *op) {
ostringstream rhs;
rhs << print_expr(op->base)
<< " + "
<< print_expr(op->stride)
<< " * "
<< print_type(op->type.with_lanes(op->lanes))
<< "(";
rhs << "0";
for (int i = 1; i < op->lanes; ++i) {
rhs << ", " << i;
}
rhs << ")";
print_assignment(op->type.with_lanes(op->lanes), rhs.str());
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Broadcast *op) {
string id_value = print_expr(op->value);
user_assert(op->value.type().lanes() == 1) << "Broadcast source must be 1-wide.\n";
ostringstream rhs;
rhs << print_type(op->type.with_lanes(op->lanes))
<< "(";
for (int i = 0; i < op->lanes; ++i) {
rhs << id_value;
if (i < op->lanes - 1) {
rhs << ", ";
}
}
rhs << ")";
print_assignment(op->type.with_lanes(op->lanes), rhs.str());
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Call *op) {
if (op->is_intrinsic(Call::gpu_thread_barrier)) {
internal_assert(op->args.size() == 1) << "gpu_thread_barrier() intrinsic must specify memory fence type.\n";
auto fence_type_ptr = as_const_int(op->args[0]);
internal_assert(fence_type_ptr) << "gpu_thread_barrier() parameter is not a constant integer.\n";
auto fence_type = *fence_type_ptr;
// By default, we'll just issue a Group (aka Shared) memory barrier,
// since it seems there isn't a sync without a memory barrier
// available
// NOTE(shoaibkamil): should we replace with AllMemoryBarrierWithGroupSync()
// if both are required?
if (fence_type & CodeGen_GPU_Dev::MemoryFenceType::Device &&
!(fence_type & CodeGen_GPU_Dev::MemoryFenceType::Shared)) {
stream << get_indent() << "DeviceMemoryBarrierWithGroupSync();\n";
} else if (fence_type & CodeGen_GPU_Dev::MemoryFenceType::Device) {
stream << get_indent() << "DeviceMemoryBarrier();\n";
}
stream << get_indent() << "GroupMemoryBarrierWithGroupSync();\n";
print_assignment(op->type, "0");
} else if (op->name == "pow_f32" && can_prove(op->args[0] > 0)) {
// If we know pow(x, y) is called with x > 0, we can use HLSL's pow
// directly.
stream << "pow(" << print_expr(op->args[0]) << ", " << print_expr(op->args[1]) << ")";
} else if (op->is_intrinsic(Call::round)) {
// HLSL's round intrinsic has the correct semantics for our rounding.
print_assignment(op->type, "round(" + print_expr(op->args[0]) + ")");
} else {
CodeGen_GPU_C::visit(op);
}
}
namespace {
// If e is a ramp expression with stride 1, return the base, otherwise undefined.
Expr is_ramp_one(const Expr &e) {
const Ramp *r = e.as<Ramp>();
if (r == nullptr) {
return Expr();
}
if (is_const_one(r->stride)) {
return r->base;
}
return Expr();
}
template<typename T>
string hex_literal(T value) {
ostringstream hex;
hex << "0x" << std::uppercase << std::setfill('0') << std::setw(8) << std::hex
<< value;
return hex.str();
}
} // namespace
struct StoragePackUnpack {
using CodeGen = CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C;
// Shader Model 5.1: threadgroup shared memory is limited 32KB
static const size_t ThreadGroupSharedStorageLimit = 32 * 1024;
void pack_storage(const Allocate *op, size_t elements, size_t size_in_bytes) {
// we could try to compact things for smaller types:
size_t packing_factor = 1;
while (size_in_bytes > ThreadGroupSharedStorageLimit) {
// must pack/unpack elements to/from shared memory...
elements = (elements + 1) & ~size_t(1);
elements /= 2;
size_in_bytes = (size_in_bytes + 1) & ~size_t(1);
size_in_bytes /= 2;
packing_factor *= 2;
}
// smallest possible pack type is a byte (no nibbles)
internal_assert(packing_factor <= 4);
}
std::ostringstream pack_store(CodeGen &cg, const Store *op) {
std::ostringstream lhs;
// NOTE(marcos): 8bit and 16bit word packing -- the smallest integer
// type granularity available in HLSL SM 5.1 is 32bit (int/uint):
Type value_type = op->value.type();
if (value_type.bits() == 32) {
// storing a 32bit word? great! just reinterpret value to uint32:
lhs << cg.print_name(op->name)
<< "[" << cg.print_expr(op->index) << "]"
<< " = "
<< cg.print_reinterpret(UInt(32), op->value)
<< ";\n";
} else {
// nightmare:
internal_assert(value_type.bits() < 32);
// must map element index to uint word array index:
ostringstream index;
auto bits = value_type.bits();
auto divisor = (32 / bits);
auto i = cg.print_expr(op->index);
index << i << " / " << divisor;
ostringstream word;
word << cg.print_name(op->name)
<< "[" + index.str() + "]";
// now mask the appropriate bits:
ostringstream mask;
mask << "("
<< hex_literal((1 << bits) - 1)
<< " << "
<< "(" << bits << "*(" << i << " % " << divisor << " ))"
<< ")";
// apply the mask to the rhs value:
ostringstream value;
value << "("
<< mask.str()
<< " & "
<< "(" << cg.print_expr(op->value) << ")"
<< ")";
// the performance impact of atomic operations on shared memory is
// not well documented... here is something:
// https://stackoverflow.com/a/19548723
lhs << cg.get_indent() << "InterlockedAnd(" << word.str() << ", "
<< "~" << mask.str() << ");\n";
lhs << cg.get_indent() << "InterlockedXor(" << word.str() << ", " << value.str() << ");\n";
}
return lhs;
}
std::ostringstream unpack_load(CodeGen &cg, const Load *op) {
std::ostringstream rhs;
// NOTE(marcos): let's keep this block of code here (disabled) in case
// we need to "emulate" byte/short packing in shared memory (recall that
// the smallest type granularity in HLSL SM 5.1 allows is 32bit types):
if (op->type.bits() == 32) {
// loading a 32bit word? great! just reinterpret as float/int/uint
rhs << "as" << cg.print_type(op->type.element_of())
<< "("
<< cg.print_name(op->name)
<< "[" << cg.print_expr(op->index) << "]"
<< ")";
} else {
// not a 32bit word? hell ensues:
internal_assert(op->type.bits() < 32);
// must map element index to uint word array index:
ostringstream index;
auto bits = op->type.bits();
auto divisor = (32 / bits);
auto i = cg.print_expr(op->index);
index << i << " / " << divisor;
ostringstream word;
word << cg.print_name(op->name)
<< "[" + index.str() + "]";
// now mask the appropriate bits:
ostringstream mask;
mask << "("
<< hex_literal((1 << bits) - 1)
<< " << "
<< "(" << bits << "*(" << i << " % " << divisor << " ))"
<< ")";
// extract the correct bits from the word
ostringstream cut;
cut << "("
<< word.str()
<< " & "
<< mask.str()
<< ")"
<< " >> "
<< "(" << bits << "*(" << i << " % " << divisor << " ))";
// if it is signed, need to propagate sign... shift-up then down:
if (op->type.is_int()) {
rhs << "asint"
<< "("
<< cut.str()
<< " << "
<< (32 - bits)
<< ")"
<< " >> "
<< (32 - bits);
} else {
rhs << cut.str();
}
}
return rhs;
}
};
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Load *op) {
user_assert(is_const_one(op->predicate)) << "Predicated load is not supported inside D3D12Compute kernel.\n";
// elements in a threadgroup shared buffer are always 32bits:
// must reinterpret (and maybe unpack) bits.
bool shared_promotion_required = false;
string promotion_str = "";
if (groupshared_allocations.contains(op->name)) {
internal_assert(allocations.contains(op->name));
Type promoted_type = op->type.with_bits(32).with_lanes(1);
if (promoted_type != op->type) {
shared_promotion_required = true;
// NOTE(marcos): might need to resort to StoragePackUnpack::unpack_load() here
promotion_str = "as" + print_type(promoted_type);
}
}
// If we're loading a contiguous ramp, "unroll" the ramp into loads:
Expr ramp_base = is_ramp_one(op->index);
if (ramp_base.defined()) {
internal_assert(op->type.is_vector());
ostringstream rhs;
rhs << print_type(op->type)
<< "(";
const int lanes = op->type.lanes();
for (int i = 0; i < lanes; ++i) {
if (shared_promotion_required) {
rhs << promotion_str << "(";
}
rhs << print_name(op->name)
<< "["
<< print_expr(ramp_base)
<< "+" << i
<< "]";
if (shared_promotion_required) {
rhs << ")";
}
if (i < lanes - 1) {
rhs << ", ";
}
}
rhs << ")";
print_assignment(op->type, rhs.str());
return;
}
string id_index = print_expr(op->index);
// Get the rhs just for the cache.
const auto *alloc = allocations.find(op->name);
bool type_cast_needed = !(alloc &&
alloc->type == op->type);
ostringstream rhs;
if (type_cast_needed) {
ostringstream element;
// Vector cases handled below
if (shared_promotion_required && !op->index.type().is_vector()) {
element << promotion_str << "(";
}
element << print_name(op->name)
<< "[" << id_index << "]";
if (shared_promotion_required && !op->index.type().is_vector()) {
element << ")";
}
Type target_type = op->type;
Type source_type = allocations.get(op->name).type;
rhs << print_cast(target_type, source_type, element.str());
} else {
// Vector cases handled below
if (shared_promotion_required && !op->index.type().is_vector()) {
rhs << promotion_str << "(";
}
rhs << print_name(op->name);
rhs << "[" << id_index << "]";
if (shared_promotion_required && !op->index.type().is_vector()) {
rhs << ")";
}
}
std::map<string, string>::iterator cached = cache.find(rhs.str());
if (cached != cache.end()) {
id = cached->second;
return;
}
if (op->index.type().is_vector()) {
// If index is a vector, gather vector elements.
internal_assert(op->type.is_vector());
// This has to be underscore as print_name prepends an underscore to
// names without one and that results in a name mismatch if a Load
// appears as the value of a Let
id = unique_name('_');
cache[rhs.str()] = id;
stream << get_indent() << print_type(op->type)
<< " " << id << ";\n";
for (int i = 0; i < op->type.lanes(); ++i) {
stream << get_indent() << id << "[" << i << "] = "
<< print_type(op->type.element_of())
<< "(";
if (shared_promotion_required) {
stream << promotion_str << "(";
}
stream << print_name(op->name)
<< "[" << id_index << "[" << i << "]]";
if (shared_promotion_required) {
stream << ")";
}
stream << ");\n";
}
} else {
print_assignment(op->type, rhs.str());
}
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Store *op) {
user_assert(is_const_one(op->predicate)) << "Predicated store is not supported inside D3D12Compute kernel.\n";
Type value_type = op->value.type();
// elements in a threadgroup shared buffer are always 32bits:
// must reinterpret (and maybe pack) bits.
bool shared_promotion_required = false;
string promotion_str = "";
if (groupshared_allocations.contains(op->name)) {
internal_assert(allocations.contains(op->name));
Type promoted_type = allocations.get(op->name).type;
if (promoted_type != op->value.type()) {
shared_promotion_required = true;
// NOTE(marcos): might need to resort to StoragePackUnpack::pack_store() here
promotion_str = "as" + print_type(promoted_type);
}
}
// If we're writing a contiguous ramp, "unroll" the ramp into stores:
Expr ramp_base = is_ramp_one(op->index);
if (ramp_base.defined()) {
internal_assert(value_type.is_vector());
int lanes = value_type.lanes();
for (int i = 0; i < lanes; ++i) {
// TODO(marcos): this indentation looks funny in the generated code
ostringstream rhs;
rhs << print_name(op->name)
<< "["
<< print_expr(ramp_base)
<< " + " << i
<< "]"
<< " = ";
if (shared_promotion_required) {
rhs << promotion_str << "(";
}
rhs << print_expr(op->value)
<< "["
<< i
<< "]";
if (shared_promotion_required) {
rhs << ")";
}
rhs << ";\n";
stream << get_indent() << rhs.str();
}
} else if (op->index.type().is_vector()) {
// If index is a vector, scatter vector elements.
internal_assert(value_type.is_vector());
for (int i = 0; i < value_type.lanes(); ++i) {
ostringstream rhs;
rhs << print_name(op->name)
<< "["
<< print_expr(op->index) << "[" << i << "]"
<< "]"
<< " = ";
if (shared_promotion_required) {
rhs << promotion_str << "(";
}
rhs << print_expr(op->value) << "[" << i << "]";
if (shared_promotion_required) {
rhs << ")";
}
rhs << ";\n";
stream << get_indent() << rhs.str();
}
} else {
ostringstream rhs;
rhs << print_name(op->name)
<< "[" << print_expr(op->index) << "]"
<< " = ";
if (shared_promotion_required) {
rhs << promotion_str << "(";
}
rhs << print_expr(op->value);
if (shared_promotion_required) {
rhs << ")";
}
rhs << ";\n";
stream << get_indent() << rhs.str();
}
cache.clear();
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Select *op) {
ostringstream rhs;
string true_val = print_expr(op->true_value);
string false_val = print_expr(op->false_value);
string cond = print_expr(op->condition);
rhs << print_type(op->type)
<< "(" << cond
<< " ? " << true_val
<< " : " << false_val
<< ")";
print_assignment(op->type, rhs.str());
}
bool is_shared_allocation(const Allocate *op) {
return op->memory_type == MemoryType::GPUShared;
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Allocate *op) {
if (is_shared_allocation(op)) {
// Already handled
internal_assert(!groupshared_allocations.contains(op->name));
groupshared_allocations.push(op->name);
op->body.accept(this);
} else {
open_scope();
debug(2) << "Allocate " << op->name << " on device\n";
debug(3) << "Pushing allocation called " << op->name << " onto the symbol table\n";
// Allocation is not a shared memory allocation, just make a local declaration.
// It must have a constant size.
int32_t size = op->constant_allocation_size();
user_assert(size > 0)
<< "Allocation " << op->name << " has a dynamic size. "
<< "Only fixed-size allocations are supported on the gpu. "
<< "Try storing into shared memory instead.";
stream << get_indent() << print_storage_type(op->type) << " "
<< print_name(op->name) << "[" << size << "];\n";
stream << get_indent();
Allocation alloc;
alloc.type = op->type;
allocations.push(op->name, alloc);
op->body.accept(this);
// Should have been freed internally
internal_assert(!allocations.contains(op->name));
close_scope("alloc " + print_name(op->name));
}
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Free *op) {
if (groupshared_allocations.contains(op->name)) {
groupshared_allocations.pop(op->name);
return;
} else {
// Should have been freed internally
internal_assert(allocations.contains(op->name));
allocations.pop(op->name);
stream << get_indent();
}
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_assignment(Type type, const string &rhs) {
string rhs_modified = print_reinforced_cast(type, rhs);
return CodeGen_GPU_C::print_assignment(type, rhs_modified);
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_vanilla_cast(Type type, const string &value_expr) {
ostringstream ss;
ss << print_type(type) << "(" << value_expr << ")";
return ss.str();
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_reinforced_cast(Type type, const string &value_expr) {
if (type.is_float() || type.is_bool() || type.bits() == 32) {
return value_expr;
}
// HLSL SM 5.1 only supports 32bit integer types; smaller integer types have
// to be placed in 32bit integers, with special attention to signed integers
// that require propagation of the sign bit (MSB):
// a) for signed types: shift-up then shift-down
// b) for unsigned types: simply mask the LSB (but shift-up and down also works)
ostringstream sl;
sl << "(" << value_expr << ")"
<< " << "
<< "(" << (32 - type.bits()) << ")"; // 1. shift-up to MSB
ostringstream rsr;
rsr << print_reinterpret_cast(type, sl.str()) // 2. reinterpret bits
<< " >> " << (32 - type.bits()); // 3. shift-down to LSB
return rsr.str();
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_reinterpret_cast(Type type, const string &value_expr) {
type = type.element_of();
string cast_expr;
cast_expr += "as";
switch (type.code()) {
case halide_type_uint:
cast_expr += "uint";
break;
case halide_type_int:
cast_expr += "int";
break;
case halide_type_float:
cast_expr += "float";
break;
case halide_type_handle:
default:
cast_expr = "BADCAST";
user_error << "Invalid reinterpret cast.\n";
break;
}
cast_expr += "(" + value_expr + ")";
return cast_expr;
}
string CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::print_cast(Type target_type, Type source_type, const string &value_expr) {
// casting to or from a float type? just use the language cast:
if (target_type.is_float() || source_type.is_float()) {
return print_vanilla_cast(target_type, value_expr);
}
// casting to or from a bool type? just use the language cast:
if (target_type.is_bool() || source_type.is_bool()) {
return print_vanilla_cast(target_type, value_expr);
}
// let the integer cast zoo begin...
internal_assert(!target_type.is_float());
internal_assert(!source_type.is_float());
// HLSL (SM 5.1) only supports 32bit integers (signed and unsigned)...
// integer downcasting-to (or upcasting-from) lower bit integers require
// some emulation in code...
internal_assert(target_type.bits() >= 8);
internal_assert(source_type.bits() >= 8);
internal_assert(target_type.bits() <= 32);
internal_assert(source_type.bits() <= 32);
internal_assert(target_type.bits() % 8 == 0);
internal_assert(source_type.bits() % 8 == 0);
// Case 1: source and target both have the same "signess"
bool same_signess = false;
same_signess |= target_type.is_int() && source_type.is_int();
same_signess |= target_type.is_uint() && source_type.is_uint();
if (same_signess) {
ostringstream ss;
if (target_type.bits() >= source_type.bits()) {
// target has enough bits to fully accommodate the source:
// it's a no-op, but we print a vanilla cast for clarity:
ss << "(" << print_vanilla_cast(target_type, value_expr) << ")";
} else {
// for signed types: shift-up then shift-down
// for unsigned types: mask the target LSB (but shift-up and down also works)
ss << "("
<< "(" << value_expr << ")"
<< " << "
<< "(" << (32 - target_type.bits()) << ")" // 1. shift-up to MSB
<< ")"
<< " >> " << (32 - target_type.bits()); // 2. shift-down to LSB
}
return ss.str();
}
// Case 2: casting from a signed source to an unsigned target
if (source_type.is_int() && target_type.is_uint()) {
// reinterpret resulting bits as uint(32):
string masked = value_expr;
if (target_type.bits() < 32) {
masked = "(" + value_expr + ")" + " & " + hex_literal((1 << target_type.bits()) - 1); // mask target LSB
}
return print_reinterpret_cast(target_type, masked);
}
// Case 3: casting from an unsigned source to a signed target
internal_assert(source_type.is_uint());
internal_assert(target_type.is_int());
ostringstream ss;
if (target_type.bits() > source_type.bits()) {
// target has enough bits to fully accommodate the source:
// it's a no-op, but we print a vanilla cast for clarity:
ss << "(" << print_vanilla_cast(target_type, value_expr) << ")";
} else {
// shift-up, reinterpret as int (target_type), then shift-down
ss << print_reinforced_cast(target_type, value_expr);
}
return ss.str();
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Cast *op) {
Type target_type = op->type;
Type source_type = op->value.type();
string cast_expr = print_cast(target_type, source_type, print_expr(op->value));
print_assignment(target_type, cast_expr);
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const Atomic *op) {
// TODO: atomics
user_assert(false) << "Atomics operations are not supported inside D3D12Compute kernel.\n";
}
void CodeGen_D3D12Compute_Dev::CodeGen_D3D12Compute_C::visit(const FloatImm *op) {
// TODO(marcos): just a pass-through for now, but we might consider doing
// something different, such as adding the suffic 'u' to the integer that
// gets passed to float_from_bits() to eliminate HLSL shader warnings; we
// have seen division-by-zero shader warnings, and we postulated that it
// could be indirectly related to compiler assumptions on signed integer
// overflow when float_from_bits() is called, but we don't know for sure
CodeGen_GPU_C::visit(op);
}
void CodeGen_D3D12Compute_Dev::add_kernel(Stmt s,
const string &name,
const vector<DeviceArgument> &args) {
debug(2) << "CodeGen_D3D12Compute_Dev::compile " << name << "\n";
// We need to scalarize/de-predicate any loads/stores, since HLSL does not
// support predication.
s = scalarize_predicated_loads_stores(s);
debug(2) << "CodeGen_D3D12Compute_Dev: after removing predication: \n"
<< s;
// TODO: do we have to uniquify these names, or can we trust that they are safe?
cur_kernel_name = name;
d3d12compute_c.add_kernel(s, name, args);
}
namespace {