Errors while compiling new DDR3 test

[pietrobressana]

Hi,

the new DDR3 test seems unable to compile, and generates the following error message:

Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/verilog/mkPcieEndpointX7.v
BSV_BO [ /home/netfpga/gitHub/connectal/bsv/HostInterface.bsv]
make[1]: *** No rule to make target obj/Ddr3Controller.bo', needed byobj/Portal.bo'. Stop.
make: *** [build.nfsume] Error 2

Thanks

[pietrobressana]

I have solved the previous issue by replacing "Ddr3Controller" with "AxiDdr3Controller" both in the BSV file and in the Makefile.

However, I can see another error message:

Error: "/home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/Ddr3Test.bsv", line 99, column 114: (T0016)
Field axiBits' is not in the typeAxiDdr3Controller::Ddr3' which was
derived for this expression.
make[1]: *** [obj/Ddr3Test.bo] Error 1
make: *** [build.nfsume] Error 2

[hanw]

I just pushed Ddr3Controller.bsv, it is modified from AxiDdr3Controller.bsv

[pietrobressana]

There is another error:

BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv]
Error: "/home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv", line 119, column 8: (T0030)
The provisos for this expression are too general.
Given type:
function m_#(SharedBuffMemServer::MemServerRead#(addrWidth, busWidth,
numClients, numServers)) f(ConnectalMemory::MemServerIndication x1,
Vector::Vector#(numMMUs, SharedBuffMMU::MMU#(addrWidth)) x2)
With the following provisos:
Add#(TLog#(TDiv#(busWidth, 8)), c__, 10)
Add#(TLog#(TDiv#(busWidth, 8)), b__, 8)
Add#(a__, addrWidth, 64)
Mul#(nrc, numClients, numServers)
IsModule#(m_, c_)
The following additional provisos are needed:
Add#(d__, TDiv#(busWidth, 8), 16)
Introduced at the following locations:
"/home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv", line 148, column 21
The type variables are from the following positions:
"d__" at "/home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv", line 148, column 21
Error: "/home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv", line 204, column 8: (T0030)
The provisos for this expression are too general.
Given type:
function m_#(SharedBuffMemServer::MemServerWrite#(addrWidth, busWidth,
numClients, numServers)) f(ConnectalMemory::MemServerIndication x1,
Vector::Vector#(numMMUs, SharedBuffMMU::MMU#(addrWidth)) x2)
With the following provisos:
Add#(TLog#(TDiv#(busWidth, 8)), c__, 10)
Add#(TLog#(TDiv#(busWidth, 8)), b__, 8)
Add#(a__, addrWidth, 64)
Mul#(nwc, numClients, numServers)
IsModule#(m_, c_)
The following additional provisos are needed:
Add#(d__, TDiv#(busWidth, 8), 16)
Introduced at the following locations:
"/home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv", line 233, column 21
The type variables are from the following positions:
"d__" at "/home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv", line 233, column 21
make[1]: *** [obj/SharedBuffMemServer.bo] Error 1
make: *** [build.nfsume] Error 2

Can you please change first line of Makefile
" CONNECTALDIR?=$(HOME)/dev/connectal "
to
" CONNECTALDIR?=$(DEV_ROOT)/connectal "
?

Thanks

[pietrobressana]

It seems that in " sonic-lite/hw/bsv/SharedBuffMemServer.bsv "

" BYTE_ENABLES " is not defined.

[pietrobressana]

By adding the provisos as suggested by the error messages, the following error message appears:

BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/Ddr3Test.bsv]
Error: "/home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/Ddr3Test.bsv", line 69, column 8: (T0031)
The provisos for this expression could not be resolved because there are no
instances of the form:
Add#(48, a__, 0)
The proviso was implied by expressions at the following positions:
"/home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/Ddr3Test.bsv", line 99, column 55
make[1]: *** [obj/Ddr3Test.bo] Error 1
make: *** [build.nfsume] Error 2

[hanw]

Pushed a fix for that.

[pietrobressana]

I have tested the design:

the SRC buffer is correctly initialized, but the program gets stuck while writing to the memory " Started writing dram ".

Therefore it is unable to read data back and to check for mismatches.

[pietrobressana]

Just downloaded the last version of the repository and re-built the example design.

The following error message is shown:

BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/generatedbsv/Top.bsv]
Error: "/home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/generatedbsv/Top.bsv", line 47, column 8: (T0108)
Module instantiation has the wrong number of arguments.
make[1]: *** [obj/Top.bo] Error 1
make: *** [build.nfsume] Error 2

[hanw]

pushed a fix

[pietrobressana]

Hi,

I have been able to compile with no errors, but the test is still not able to read back the data.
It gets stuck while writing to dram.

[hanw]

Hi Pietro,

The example gives you MemWriteClient and MemReadClient interface that you can directly use to write/read to DDR memory. But you would need to complete the example by actually sending a write request or read request to the MemWriteClient/ReadClient interface fifos.

[pietrobressana]

Hi,

the last update of DDR3 example is not able to compile:

BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/bsv/SharedBuffMemServer.bsv]
BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/generatedbsv/MemServerIndication.bsv]
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationInput.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationInput.v
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationWrapperMemPortalPipes.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationWrapperMemPortalPipes.v
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationOutputPipes.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationOutputPipes.v
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationOutput.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationOutput.v
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationProxySynth.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationProxySynth.v
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationInverter.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationInverter.v
Schedule dump file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/obj/mkMemServerIndicationInverterV.sched
Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/nfsume/verilog/mkMemServerIndicationInverterV.v
BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/Ddr3Test.bsv]
Error: "/home/netfpga/gitHub/sonic-lite/hw/tests/new_test_ddr3/Ddr3Test.bsv", line 97, column 31: (T0004)
Unbound variable `mkSimpleMMU'
make[1]: *** [obj/Ddr3Test.bo] Error 1
make: *** [build.nfsume] Error 2

[pietrobressana]

Adding the following line to "Ddr3Test.bsv" solves the previous issue:

import MMU::*;

now, a new error message appears:

Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/verilog/mkMemServerIndicationInverterV.v
BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/Ddr3Test.bsv]
Error: "/home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/Ddr3Test.bsv", line 99, column 102: (T0031)
The provisos for this expression could not be resolved because there are no
instances of the form:
BuildVector::BuildVector#(MMU::MMU#(30), Vector::Vector#(a__, SharedBuffMMU::MMU#(30)), 0)
make[1]: *** [obj/Ddr3Test.bo] Error 1
make: *** [build.nfsume] Error 2

[hanw]

pushed changes to SharedBuffMMU.

[pietrobressana]

New error message:

Verilog file created: /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/verilog/mkDdr3TestRequestInverterV.v
BSV_BO [ /home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/generatedbsv/Top.bsv]
Error: "/home/netfpga/gitHub/sonic-lite/hw/tests/test_ddr3/nfsume/generatedbsv/Top.bsv", line 50, column 8: (T0108)
Module instantiation has the wrong number of arguments.
make[1]: *** [obj/Top.bo] Error 1
make: *** [build.nfsume] Error 2