Skip to content

Commit 2c10e6a

Browse files
HiFiPhileHiFiPhile
committed
bsp/imxrt: refresh teensy config
Signed-off-by: HiFiPhile <admin@hifiphile.com>
1 parent 6252448 commit 2c10e6a

File tree

10 files changed

+146
-208
lines changed

10 files changed

+146
-208
lines changed

‎hw/bsp/imxrt/boards/teensy_40/board/clock_config.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -15,11 +15,11 @@
1515

1616
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
1717
!!GlobalInfo
18-
product: Clocks v11.0
18+
product: Clocks v20.0
1919
processor: MIMXRT1062xxxxA
2020
package_id: MIMXRT1062DVL6A
2121
mcu_data: ksdk2_0
22-
processor_version: 13.0.2
22+
processor_version: 26.03.10
2323
board: MIMXRT1060-EVK
2424
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
2525

‎hw/bsp/imxrt/boards/teensy_40/board/clock_config.h‎

Lines changed: 50 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -36,56 +36,56 @@ void BOARD_InitBootClocks(void);
3636
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
3737

3838
/* Clock outputs (values are in Hz): */
39-
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
40-
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
41-
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
42-
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
43-
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
44-
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
45-
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
46-
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
47-
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL
48-
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL
49-
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL
50-
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
51-
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
52-
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
53-
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
54-
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
55-
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
56-
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL
57-
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL
58-
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
59-
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
60-
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
61-
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
62-
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
63-
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
64-
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
65-
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
66-
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
67-
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL
68-
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
69-
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
70-
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
71-
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
72-
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
73-
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
74-
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
75-
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
76-
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
77-
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
78-
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
79-
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
80-
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
81-
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
82-
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
83-
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
84-
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
85-
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL
86-
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL
87-
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
88-
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
39+
#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */
40+
#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */
41+
#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */
42+
#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
43+
#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
44+
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
45+
#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
46+
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */
47+
#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */
48+
#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */
49+
#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */
50+
#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */
51+
#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */
52+
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */
53+
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */
54+
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
55+
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */
56+
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */
57+
#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
58+
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
59+
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
60+
#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */
61+
#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */
62+
#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */
63+
#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */
64+
#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */
65+
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
66+
#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
67+
#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */
68+
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
69+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
70+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
71+
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
72+
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */
73+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */
74+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */
75+
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */
76+
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
77+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
78+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
79+
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
80+
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */
81+
#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
82+
#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
83+
#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
84+
#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */
85+
#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */
86+
#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */
87+
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */
88+
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */
8989

9090
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
9191
*/

‎hw/bsp/imxrt/boards/teensy_40/board/pin_mux.c‎

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@
66
/*
77
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
88
!!GlobalInfo
9-
product: Pins v13.1
9+
product: Pins v17.0
1010
processor: MIMXRT1062xxxxA
1111
package_id: MIMXRT1062DVL6A
1212
mcu_data: ksdk2_0
13-
processor_version: 13.0.2
13+
processor_version: 26.03.10
1414
board: MIMXRT1060-EVK
1515
pin_labels:
1616
- {pin_num: E7, pin_signal: GPIO_B0_01, label: LCDIF_ENABLE, identifier: USER_BUTTON}
@@ -80,16 +80,13 @@ void BOARD_InitPins(void) {
8080
IOMUXC_SetPinConfig(IOMUXC_GPIO_B0_01_GPIO2_IO01, 0xB0B0U);
8181
}
8282

83-
8483
/*
8584
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
8685
BOARD_InitDEBUG_UARTPins:
8786
- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
8887
- pin_list:
89-
- {pin_num: K14, peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_12, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
90-
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
91-
- {pin_num: L14, peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_13, software_input_on: Disable, hysteresis_enable: Disable, pull_up_down_config: Pull_Down_100K_Ohm,
92-
pull_keeper_select: Keeper, pull_keeper_enable: Enable, open_drain: Disable, speed: MHZ_100, drive_strength: R0_6, slew_rate: Slow}
88+
- {pin_num: G11, peripheral: LPUART6, signal: RX, pin_signal: GPIO_AD_B0_03, speed: MHZ_50}
89+
- {pin_num: M11, peripheral: LPUART6, signal: TX, pin_signal: GPIO_AD_B0_02, speed: MHZ_50}
9390
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
9491
*/
9592

@@ -104,11 +101,10 @@ void BOARD_InitDEBUG_UARTPins(void) {
104101

105102
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_02_LPUART6_TX, 0U);
106103
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_03_LPUART6_RX, 0U);
107-
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPUART6_TX, 0x10B0U);
108-
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPUART6_RX, 0x10B0U);
104+
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_02_LPUART6_TX, 0x1030U);
105+
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_03_LPUART6_RX, 0x1030U);
109106
}
110107

111-
112108
/*
113109
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
114110
BOARD_InitUSDHCPins:
@@ -142,7 +138,6 @@ void BOARD_InitUSDHCPins(void) {
142138
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U);
143139
}
144140

145-
146141
/*
147142
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
148143
BOARD_InitQSPIPins:
@@ -175,7 +170,6 @@ void BOARD_InitQSPIPins(void) {
175170
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U);
176171
IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U);
177172
}
178-
179173
/***********************************************************************************************************************
180174
* EOF
181175
**********************************************************************************************************************/

‎hw/bsp/imxrt/boards/teensy_40/board/pin_mux.h‎

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ void BOARD_InitBootPins(void);
4747

4848
/* Symbols to be used with GPIO driver */
4949
#define BOARD_INITPINS_USER_LED_GPIO GPIO2 /*!< GPIO peripheral base pointer */
50+
#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */
5051
#define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */
5152
#define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
5253
#define BOARD_INITPINS_USER_LED_PORT GPIO2 /*!< PORT peripheral base pointer */
@@ -73,16 +74,6 @@ void BOARD_InitBootPins(void);
7374
*/
7475
void BOARD_InitPins(void);
7576

76-
/* GPIO_AD_B0_12 (coord K14), UART1_TXD */
77-
/* Routed pin properties */
78-
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
79-
#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */
80-
81-
/* GPIO_AD_B0_13 (coord L14), UART1_RXD */
82-
/* Routed pin properties */
83-
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
84-
#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */
85-
8677
/*!
8778
* @brief Configures pin routing and optionally pin electrical features.
8879
*

0 commit comments

Comments
 (0)