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Commit 380bfc0

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hathachhathach
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fix portenta build, added core-m85.cmake/mk
1 parent ad0ac67 commit 380bfc0

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8 files changed

+179
-16
lines changed

8 files changed

+179
-16
lines changed

‎examples/build_system/cmake/cpu/cortex-m85.cmake‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
1+
if (TOOLCHAIN STREQUAL "gcc")
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set(TOOLCHAIN_COMMON_FLAGS
3+
-mthumb
4+
-mcpu=cortex-m85
5+
-mfloat-abi=hard
6+
-mfpu=fpv5-d16
7+
)
8+
set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
9+
10+
elseif (TOOLCHAIN STREQUAL "clang")
11+
set(TOOLCHAIN_COMMON_FLAGS
12+
--target=arm-none-eabi
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-mcpu=cortex-m85
14+
-mfpu=fpv5-d16
15+
)
16+
set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
17+
18+
elseif (TOOLCHAIN STREQUAL "iar")
19+
set(TOOLCHAIN_COMMON_FLAGS
20+
--cpu cortex-m85
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--fpu VFPv5_D16
22+
)
23+
set(FREERTOS_PORT IAR_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
24+
25+
endif ()

‎examples/build_system/make/cpu/cortex-m85.mk‎

Lines changed: 27 additions & 0 deletions
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1+
ifeq ($(TOOLCHAIN),gcc)
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CFLAGS += \
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-mthumb \
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-mcpu=cortex-m85 \
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-mfloat-abi=hard \
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-mfpu=fpv5-d16 \
7+
8+
else ifeq ($(TOOLCHAIN),clang)
9+
CFLAGS += \
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--target=arm-none-eabi \
11+
-mcpu=cortex-m85 \
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-mfpu=fpv5-d16 \
13+
14+
else ifeq ($(TOOLCHAIN),iar)
15+
CFLAGS += \
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--cpu cortex-m85 \
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--fpu VFPv5_D16 \
18+
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ASFLAGS += \
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--cpu cortex-m85 \
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--fpu VFPv5_D16 \
22+
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else
24+
$(error "TOOLCHAIN is not supported")
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endif
26+
27+
FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM85_NTZ/non_secure

‎hw/bsp/ra/boards/portenta_c33/board.cmake‎

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -4,22 +4,13 @@ set(MCU_VARIANT ra6m5)
44
set(JLINK_DEVICE R7FA6M5BH)
55
set(DFU_UTIL_VID_PID 2341:0368)
66

7-
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
8-
9-
# Device port default to PORT1 Highspeed
10-
if (NOT DEFINED PORT)
11-
set(PORT 1)
7+
# device default to PORT 1 High Speed
8+
if (NOT DEFINED RHPORT_DEVICE)
9+
set(RHPORT_DEVICE 1)
10+
endif()
11+
if (NOT DEFINED RHPORT_HOST)
12+
set(RHPORT_HOST 0)
1213
endif()
13-
14-
# Host port will be the other port
15-
set(HOST_PORT $<NOT:${PORT}>)
1614

1715
function(update_board TARGET)
18-
target_compile_definitions(${TARGET} PUBLIC
19-
BOARD_TUD_RHPORT=${PORT}
20-
BOARD_TUH_RHPORT=${HOST_PORT}
21-
# port 0 is fullspeed, port 1 is highspeed
22-
BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
23-
BOARD_TUH_MAX_SPEED=$<IF:${HOST_PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
24-
)
2516
endfunction()

‎hw/bsp/ra/boards/portenta_c33/board.mk‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@ CPU_CORE = cortex-m33
22
MCU_VARIANT = ra6m5
33

44
# Port 1 is highspeed
5-
PORT ?= 1
5+
RHPORT_DEVICE ?= 1
6+
RHPORT_HOST ?= 0
67

78
JLINK_DEVICE = R7FA6M5BH
89
DFU_UTIL_OPTION = -d 2341:0368 -a 0

‎hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
/* generated configuration header file - do not edit */
2+
#ifndef BSP_PIN_CFG_H_
3+
#define BSP_PIN_CFG_H_
4+
#include "r_ioport.h"
5+
6+
/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
7+
FSP_HEADER
8+
9+
#define LED1 (BSP_IO_PORT_01_PIN_07)
10+
#define SW1 (BSP_IO_PORT_04_PIN_08)
11+
extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
12+
13+
void BSP_PinConfigSecurityInit();
14+
15+
/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
16+
FSP_FOOTER
17+
#endif /* BSP_PIN_CFG_H_ */

‎hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
/* generated common source file - do not edit */
2+
#include "common_data.h"
3+
ioport_instance_ctrl_t g_ioport_ctrl;
4+
const ioport_instance_t g_ioport =
5+
{
6+
.p_api = &g_ioport_on_ioport,
7+
.p_ctrl = &g_ioport_ctrl,
8+
.p_cfg = &g_bsp_pin_cfg,
9+
};
10+
void g_common_init(void) {
11+
}

‎hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
/* generated common header file - do not edit */
2+
#ifndef COMMON_DATA_H_
3+
#define COMMON_DATA_H_
4+
#include <stdint.h>
5+
#include "bsp_api.h"
6+
#include "r_ioport.h"
7+
#include "bsp_pin_cfg.h"
8+
FSP_HEADER
9+
#define IOPORT_CFG_NAME g_bsp_pin_cfg
10+
#define IOPORT_CFG_OPEN R_IOPORT_Open
11+
#define IOPORT_CFG_CTRL g_ioport_ctrl
12+
13+
/* IOPORT Instance */
14+
extern const ioport_instance_t g_ioport;
15+
16+
/* IOPORT control structure. */
17+
extern ioport_instance_ctrl_t g_ioport_ctrl;
18+
void g_common_init(void);
19+
FSP_FOOTER
20+
#endif /* COMMON_DATA_H_ */

‎hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c‎

Lines changed: 71 additions & 0 deletions
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@@ -0,0 +1,71 @@
1+
/* generated pin source file - do not edit */
2+
#include "bsp_api.h"
3+
#include "r_ioport.h"
4+
5+
6+
const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
7+
{
8+
.pin = BSP_IO_PORT_01_PIN_07,
9+
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
10+
},
11+
{
12+
.pin = BSP_IO_PORT_01_PIN_08,
13+
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
14+
},
15+
{
16+
.pin = BSP_IO_PORT_03_PIN_00,
17+
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
18+
},
19+
{
20+
.pin = BSP_IO_PORT_04_PIN_07,
21+
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
22+
},
23+
{
24+
.pin = BSP_IO_PORT_04_PIN_08,
25+
.pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
26+
},
27+
{
28+
.pin = BSP_IO_PORT_11_PIN_01,
29+
.pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
30+
},
31+
};
32+
33+
const ioport_cfg_t g_bsp_pin_cfg = {
34+
.number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
35+
.p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
36+
};
37+
38+
#if BSP_TZ_SECURE_BUILD
39+
40+
void R_BSP_PinCfgSecurityInit(void);
41+
42+
/* Initialize SAR registers for secure pins. */
43+
void R_BSP_PinCfgSecurityInit(void)
44+
{
45+
#if (2U == BSP_FEATURE_IOPORT_VERSION)
46+
uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
47+
#else
48+
uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
49+
#endif
50+
memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
51+
52+
53+
for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
54+
{
55+
uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
56+
uint32_t port = port_pin >> 8U;
57+
uint32_t pin = port_pin & 0xFFU;
58+
pmsar[port] &= (uint16_t) ~(1U << pin);
59+
}
60+
61+
for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
62+
{
63+
#if (2U == BSP_FEATURE_IOPORT_VERSION)
64+
R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
65+
#else
66+
R_PMISC->PMSAR[i].PMSAR = pmsar[i];
67+
#endif
68+
}
69+
70+
}
71+
#endif

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