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Move BOARD_ConfigMPU into board specific init
Signed-off-by: HiFiPhile <[email protected]>
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‎hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h‎

Lines changed: 389 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,4 +49,393 @@
4949
#define UART_PORT LPUART1
5050
#define UART_CLK_ROOT BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT
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52+
// Additional board init for MPU configuration
53+
#define BOARD_INIT_2 1
54+
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//--------------------------------------------------------------------
56+
// MPU configuration
57+
//--------------------------------------------------------------------
58+
#if __CORTEX_M == 7
59+
static void BOARD_ConfigMPU(void) {
60+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
61+
extern uint32_t Image$$RW_m_ncache$$Base[];
62+
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
63+
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
64+
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
65+
uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
66+
uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
67+
#elif defined(__MCUXPRESSO)
68+
#if defined(__USE_SHMEM)
69+
extern uint32_t __base_rpmsg_sh_mem;
70+
extern uint32_t __top_rpmsg_sh_mem;
71+
uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem);
72+
uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart;
73+
#else
74+
extern uint32_t __base_NCACHE_REGION;
75+
extern uint32_t __top_NCACHE_REGION;
76+
uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
77+
uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
78+
#endif
79+
#elif defined(__ICCARM__) || defined(__GNUC__)
80+
extern uint32_t __NCACHE_REGION_START[];
81+
extern uint32_t __NCACHE_REGION_SIZE[];
82+
uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
83+
uint32_t size = (uint32_t) __NCACHE_REGION_SIZE;
84+
#endif
85+
volatile uint32_t i = 0;
86+
87+
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
88+
/* Disable I cache and D cache */
89+
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) {
90+
SCB_DisableICache();
91+
}
92+
#endif
93+
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
94+
if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) {
95+
SCB_DisableDCache();
96+
}
97+
#endif
98+
99+
/* Disable MPU */
100+
ARM_MPU_Disable();
101+
102+
/* MPU configure:
103+
* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
104+
* SubRegionDisable, Size)
105+
* API in mpu_armv7.h.
106+
* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
107+
* disabled.
108+
* param AccessPermission Data access permissions, allows you to configure read/write access for User and
109+
* Privileged mode.
110+
* Use MACROS defined in mpu_armv7.h:
111+
* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
112+
* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
113+
* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
114+
* 0 x 0 0 Strongly Ordered shareable
115+
* 0 x 0 1 Device shareable
116+
* 0 0 1 0 Normal not shareable Outer and inner write
117+
* through no write allocate
118+
* 0 0 1 1 Normal not shareable Outer and inner write
119+
* back no write allocate
120+
* 0 1 1 0 Normal shareable Outer and inner write
121+
* through no write allocate
122+
* 0 1 1 1 Normal shareable Outer and inner write
123+
* back no write allocate
124+
* 1 0 0 0 Normal not shareable outer and inner
125+
* noncache
126+
* 1 1 0 0 Normal shareable outer and inner
127+
* noncache
128+
* 1 0 1 1 Normal not shareable outer and inner write
129+
* back write/read acllocate
130+
* 1 1 1 1 Normal shareable outer and inner write
131+
* back write/read acllocate
132+
* 2 x 0 0 Device not shareable
133+
* Above are normal use settings, if your want to see more details or want to config different inner/outer cache
134+
* policy.
135+
* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
136+
* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
137+
* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
138+
* mpu_armv7.h.
139+
*/
140+
141+
/*
142+
* Add default region to deny access to whole address space to workaround speculative prefetch.
143+
* Refer to Arm errata 1013783-B for more details.
144+
*
145+
*/
146+
/* Region 0 setting: Instruction access disabled, No data access permission. */
147+
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
148+
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
149+
150+
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
151+
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
152+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
153+
154+
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
155+
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
156+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
157+
158+
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
159+
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
160+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
161+
162+
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
163+
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
164+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
165+
166+
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
167+
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
168+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
169+
170+
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
171+
/* Region 6 setting: Memory with Normal type, not shareable, write through */
172+
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
173+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
174+
175+
/* Region 7 setting: Memory with Normal type, not shareable, write through */
176+
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
177+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
178+
#else
179+
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
180+
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
181+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB);
182+
183+
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
184+
MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U);
185+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
186+
#endif
187+
188+
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
189+
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */
190+
MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U);
191+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
192+
#endif
193+
194+
#ifdef USE_SDRAM
195+
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
196+
/* Region 9 setting: Memory with Normal type, not shareable, write through */
197+
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
198+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
199+
#else
200+
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
201+
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
202+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB);
203+
#endif
204+
#endif
205+
206+
while ((size >> i) > 0x1U) {
207+
i++;
208+
}
209+
210+
if (i != 0) {
211+
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
212+
assert(!(nonCacheStart % size));
213+
assert(size == (uint32_t) (1 << i));
214+
assert(i >= 5);
215+
216+
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
217+
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
218+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
219+
}
220+
221+
/* Region 11 setting: Memory with Device type, not shareable, non-cacheable */
222+
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
223+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
224+
225+
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
226+
MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000);
227+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
228+
229+
/* Region 13 setting: Memory with Device type, not shareable, non-cacheable */
230+
MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000);
231+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
232+
233+
/* Region 14 setting: Memory with Device type, not shareable, non-cacheable */
234+
MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000);
235+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
236+
237+
/* Region 15 setting: Memory with Device type, not shareable, non-cacheable */
238+
MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000);
239+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
240+
241+
/* Enable MPU */
242+
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
243+
244+
/* Enable I cache and D cache */
245+
#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
246+
SCB_EnableDCache();
247+
#endif
248+
#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
249+
SCB_EnableICache();
250+
#endif
251+
}
252+
253+
#elif __CORTEX_M == 4
254+
255+
static void BOARD_ConfigMPU(void) {
256+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
257+
extern uint32_t Image$$RW_m_ncache$$Base[];
258+
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
259+
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
260+
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
261+
uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base;
262+
uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
263+
#elif defined(__MCUXPRESSO)
264+
extern uint32_t __base_NCACHE_REGION;
265+
extern uint32_t __top_NCACHE_REGION;
266+
uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION);
267+
uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart;
268+
#elif defined(__ICCARM__) || defined(__GNUC__)
269+
extern uint32_t __NCACHE_REGION_START[];
270+
extern uint32_t __NCACHE_REGION_SIZE[];
271+
uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START;
272+
uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE;
273+
#endif
274+
#if defined(__USE_SHMEM)
275+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
276+
extern uint32_t Image$$RPMSG_SH_MEM$$Base[];
277+
/* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */
278+
extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[];
279+
extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[];
280+
uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base;
281+
uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart;
282+
#elif defined(__MCUXPRESSO)
283+
extern uint32_t __base_rpmsg_sh_mem;
284+
extern uint32_t __top_rpmsg_sh_mem;
285+
uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem);
286+
uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart;
287+
#elif defined(__ICCARM__) || defined(__GNUC__)
288+
extern uint32_t __RPMSG_SH_MEM_START[];
289+
extern uint32_t __RPMSG_SH_MEM_SIZE[];
290+
uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START;
291+
uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE;
292+
#endif
293+
#endif
294+
uint32_t i = 0;
295+
296+
/* Only config non-cacheable region on system bus */
297+
assert(nonCacheStart >= 0x20000000);
298+
299+
/* Disable code bus cache */
300+
if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) {
301+
/* Enable the processor code bus to push all modified lines. */
302+
LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK;
303+
/* Wait until the cache command completes. */
304+
while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
305+
}
306+
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
307+
LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK);
308+
/* Now disable the cache. */
309+
LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK;
310+
}
311+
312+
/* Disable system bus cache */
313+
if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) {
314+
/* Enable the processor system bus to push all modified lines. */
315+
LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK;
316+
/* Wait until the cache command completes. */
317+
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
318+
}
319+
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
320+
LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK);
321+
/* Now disable the cache. */
322+
LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK;
323+
}
324+
325+
/* Disable MPU */
326+
ARM_MPU_Disable();
327+
328+
#if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH
329+
/* Region 0 setting: Memory with Normal type, not shareable, write through */
330+
MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U);
331+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB);
332+
333+
/* Region 1 setting: Memory with Normal type, not shareable, write through */
334+
MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U);
335+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB);
336+
337+
/* Region 2 setting: Memory with Normal type, not shareable, write through */
338+
MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U);
339+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB);
340+
341+
while ((nonCacheSize >> i) > 0x1U) {
342+
i++;
343+
}
344+
345+
if (i != 0) {
346+
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
347+
assert(!(nonCacheStart % nonCacheSize));
348+
assert(nonCacheSize == (uint32_t) (1 << i));
349+
assert(i >= 5);
350+
351+
/* Region 3 setting: Memory with device type, not shareable, non-cacheable */
352+
MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart);
353+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
354+
}
355+
356+
#if defined(__USE_SHMEM)
357+
i = 0;
358+
359+
while ((rpmsgShmemSize >> i) > 0x1U) {
360+
i++;
361+
}
362+
363+
if (i != 0) {
364+
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
365+
assert(!(rpmsgShmemStart % rpmsgShmemSize));
366+
assert(rpmsgShmemSize == (uint32_t) (1 << i));
367+
assert(i >= 5);
368+
369+
/* Region 4 setting: Memory with device type, not shareable, non-cacheable */
370+
MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart);
371+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
372+
}
373+
#endif
374+
#else
375+
while ((nonCacheSize >> i) > 0x1U) {
376+
i++;
377+
}
378+
379+
if (i != 0) {
380+
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
381+
assert(!(nonCacheStart % nonCacheSize));
382+
assert(nonCacheSize == (uint32_t) (1 << i));
383+
assert(i >= 5);
384+
385+
/* Region 0 setting: Memory with device type, not shareable, non-cacheable */
386+
MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart);
387+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
388+
}
389+
390+
#if defined(__USE_SHMEM)
391+
i = 0;
392+
393+
while ((rpmsgShmemSize >> i) > 0x1U) {
394+
i++;
395+
}
396+
397+
if (i != 0) {
398+
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
399+
assert(!(rpmsgShmemStart % rpmsgShmemSize));
400+
assert(rpmsgShmemSize == (uint32_t) (1 << i));
401+
assert(i >= 5);
402+
403+
/* Region 1 setting: Memory with device type, not shareable, non-cacheable */
404+
MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart);
405+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1);
406+
}
407+
#endif
408+
#endif
409+
410+
/* Enable MPU */
411+
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
412+
413+
/* Enables the processor system bus to invalidate all lines in both ways.
414+
and Initiate the processor system bus cache command. */
415+
LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK;
416+
/* Wait until the cache command completes */
417+
while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) {
418+
}
419+
/* As a precaution clear the bits to avoid inadvertently re-running this command. */
420+
LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK);
421+
/* Now enable the system bus cache. */
422+
LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK;
423+
424+
/* Enables the processor code bus to invalidate all lines in both ways.
425+
and Initiate the processor code bus code cache command. */
426+
LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK;
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/* Wait until the cache command completes. */
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while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) {
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}
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/* As a precaution clear the bits to avoid inadvertently re-running this command. */
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LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK);
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/* Now enable the code bus cache. */
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LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK;
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}
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#endif
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static void board_init2() {
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BOARD_ConfigMPU();
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}
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52441
#endif

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