@@ -36,36 +36,36 @@ void BOARD_InitBootClocks(void);
3636#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
3737
3838/* Clock outputs (values are in Hz): */
39- #define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL
40- #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
41- #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
42- #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
43- #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
44- #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
45- #define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL
46- #define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
47- #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
48- #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
49- #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
50- #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
51- #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
52- #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
53- #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
54- #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
55- #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
56- #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
57- #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
58- #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
59- #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
60- #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
61- #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
62- #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
63- #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
64- #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
65- #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
66- #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
67- #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
68- #define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL
39+ #define BOARD_BOOTCLOCKRUN_ADC_ALT_CLK 40000000UL /* Clock consumers of ADC_ALT_CLK output : N/A */
40+ #define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */
41+ #define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */
42+ #define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */
43+ #define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */
44+ #define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */
45+ #define BOARD_BOOTCLOCKRUN_CORE_CLK_ROOT 500000000UL /* Clock consumers of CORE_CLK_ROOT output : ARM, FLEXSPI */
46+ #define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */
47+ #define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */
48+ #define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */
49+ #define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */
50+ #define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */
51+ #define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AIPSTZ1, AIPSTZ2, AOI, ARM, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, OCOTP, PWM1, RTWDOG, SAI1, SAI3, SNVS, SPDIF, SRC, TEMPMON, TRNG, USB, WDOG1, WDOG2, XBARA */
52+ #define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */
53+ #define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */
54+ #define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */
55+ #define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */
56+ #define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */
57+ #define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */
58+ #define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */
59+ #define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */
60+ #define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */
61+ #define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */
62+ #define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */
63+ #define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */
64+ #define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */
65+ #define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */
66+ #define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */
67+ #define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */
68+ #define BOARD_BOOTCLOCKRUN_USBPHY_CLK 480000000UL /* Clock consumers of USBPHY_CLK output : TEMPMON, USB */
6969
7070/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
7171 */
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