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hathachhathach
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change dcd_dcache_*() API return type from void to bool
1 parent 66741e3 commit 833eb7d

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8 files changed

+67
-65
lines changed

8 files changed

+67
-65
lines changed

‎src/common/tusb_mcu.h‎

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -364,19 +364,15 @@
364364
#define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep
365365

366366
#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
367+
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64
367368

368369
#if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
369370
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
370371
#endif
371372

372-
#if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1
373-
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
374-
#endif
375-
376-
#define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 64
377-
#define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 64
373+
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
374+
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 0
378375

379-
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif
380376

381377
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
382378
#if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))

‎src/common/tusb_types.h‎

Lines changed: 22 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,9 @@
3535
extern "C" {
3636
#endif
3737

38-
#define TUD_EPBUF_DCACHE_SIZE(_size) \
39-
(CFG_TUD_MEM_DCACHE_ENABLE ? (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
38+
//------------- Device DCache declaration -------------//
39+
#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \
40+
(TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size))
4041

4142
// Declare an endpoint buffer with uint8_t[size]
4243
#define TUD_EPBUF_DEF(_name, _size) \
@@ -52,6 +53,25 @@
5253
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
5354
};
5455

56+
//------------- Host DCache declaration -------------//
57+
#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
58+
(TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size))
59+
60+
// Declare an endpoint buffer with uint8_t[size]
61+
#define TUH_EPBUF_DEF(_name, _size) \
62+
union { \
63+
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
64+
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
65+
};
66+
67+
// Declare an endpoint buffer with a type
68+
#define TUH_EPBUF_TYPE_DEF(_name, _type) \
69+
union { \
70+
CFG_TUH_MEM_ALIGN _type _name; \
71+
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
72+
};
73+
74+
5575
/*------------------------------------------------------------------*/
5676
/* CONSTANTS
5777
*------------------------------------------------------------------*/

‎src/device/dcd.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {
9393

9494
// clean/flush data cache: write cache -> memory.
9595
// Required before an DMA TX transfer to make sure data is in memory
96-
void dcd_dcache_clean(const void* addr, uint32_t data_size);
96+
bool dcd_dcache_clean(const void* addr, uint32_t data_size);
9797

9898
// invalidate data cache: mark cache as invalid, next read will read from memory
9999
// Required BOTH before and after an DMA RX transfer
100-
void dcd_dcache_invalidate(const void* addr, uint32_t data_size);
100+
bool dcd_dcache_invalidate(const void* addr, uint32_t data_size);
101101

102102
// clean and invalidate data cache
103103
// Required before an DMA transfer where memory is both read/write by DMA
104-
void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
104+
bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
105105

106106
//--------------------------------------------------------------------+
107107
// Controller API

‎src/device/usbd.c‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -97,16 +97,19 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
9797
(void) rhport;
9898
}
9999

100-
TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) {
100+
TU_ATTR_WEAK bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
101101
(void) addr; (void) data_size;
102+
return true;
102103
}
103104

104-
TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
105+
TU_ATTR_WEAK bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
105106
(void) addr; (void) data_size;
107+
return true;
106108
}
107109

108-
TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
110+
TU_ATTR_WEAK bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
109111
(void) addr; (void) data_size;
112+
return true;
110113
}
111114

112115
//--------------------------------------------------------------------+

‎src/portable/chipidea/ci_hs/dcd_ci_hs.c‎

Lines changed: 8 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -34,43 +34,29 @@
3434
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX
3535
#include "ci_hs_imxrt.h"
3636

37-
void dcd_dcache_clean(void const* addr, uint32_t data_size) {
38-
imxrt_dcache_clean(addr, data_size);
37+
bool dcd_dcache_clean(void const* addr, uint32_t data_size) {
38+
return imxrt_dcache_clean(addr, data_size);
3939
}
4040

41-
void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
42-
imxrt_dcache_invalidate(addr, data_size);
41+
bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
42+
return imxrt_dcache_invalidate(addr, data_size);
4343
}
4444

45-
void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
46-
imxrt_dcache_clean_invalidate(addr, data_size);
45+
bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
46+
return imxrt_dcache_clean_invalidate(addr, data_size);
4747
}
4848

49-
#else
50-
51-
#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
49+
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
5250
#include "ci_hs_lpc18_43.h"
5351

5452
#elif TU_CHECK_MCU(OPT_MCU_MCXN9)
5553
// MCX N9 only port 1 use this controller
5654
#include "ci_hs_mcx.h"
55+
5756
#else
5857
#error "Unsupported MCUs"
5958
#endif
6059

61-
TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) {
62-
(void) addr; (void) data_size;
63-
}
64-
65-
TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) {
66-
(void) addr; (void) data_size;
67-
}
68-
69-
TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) {
70-
(void) addr; (void) data_size;
71-
}
72-
#endif
73-
7460
//--------------------------------------------------------------------+
7561
// MACRO CONSTANT TYPEDEF
7662
//--------------------------------------------------------------------+

‎src/portable/synopsys/dwc2/dcd_dwc2.c‎

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -83,22 +83,19 @@ CFG_TUD_MEM_SECTION static struct {
8383
// DMA
8484
//--------------------------------------------------------------------
8585
#if CFG_TUD_MEM_DCACHE_ENABLE
86-
void dcd_dcache_clean(const void* addr, uint32_t data_size) {
87-
if (addr && data_size) {
88-
dwc2_dcache_clean(addr, data_size);
89-
}
86+
bool dcd_dcache_clean(const void* addr, uint32_t data_size) {
87+
TU_VERIFY(addr && data_size);
88+
return dwc2_dcache_clean(addr, data_size);
9089
}
9190

92-
void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
93-
if (addr && data_size) {
94-
dwc2_dcache_invalidate(addr, data_size);
95-
}
91+
bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
92+
TU_VERIFY(addr && data_size);
93+
return dwc2_dcache_invalidate(addr, data_size);
9694
}
9795

98-
void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
99-
if (addr && data_size) {
100-
dwc2_dcache_clean_invalidate(addr, data_size);
101-
}
96+
bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
97+
TU_VERIFY(addr && data_size);
98+
return dwc2_dcache_clean_invalidate(addr, data_size);
10299
}
103100
#endif
104101

‎src/portable/synopsys/dwc2/dwc2_esp32.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -130,22 +130,22 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_
130130
return size;
131131
}
132132

133-
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) {
133+
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(const void* addr, uint32_t data_size) {
134134
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M;
135135
data_size = round_up_to_cache_line_size(data_size);
136-
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
136+
return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
137137
}
138138

139-
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
139+
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
140140
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
141141
data_size = round_up_to_cache_line_size(data_size);
142-
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
142+
return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
143143
}
144144

145-
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
145+
TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
146146
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
147147
data_size = round_up_to_cache_line_size(data_size);
148-
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
148+
return ESP_OK == esp_cache_msync((void*)addr, data_size, flag);
149149
}
150150

151151
#endif

‎src/tusb_option.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -397,6 +397,14 @@
397397
#define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4)
398398
#endif
399399

400+
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE
401+
#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
402+
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32
403+
#endif
404+
405+
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT
406+
#endif
407+
400408
// OS selection
401409
#ifndef CFG_TUSB_OS
402410
#define CFG_TUSB_OS OPT_OS_NONE
@@ -433,11 +441,7 @@
433441
#endif
434442

435443
#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE
436-
#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT
437-
#define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 32
438-
#endif
439-
440-
#define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT
444+
#define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
441445
#endif
442446

443447
#ifndef CFG_TUD_ENDPOINT0_SIZE
@@ -556,11 +560,7 @@
556560
#endif
557561

558562
#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE
559-
#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT
560-
#define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 32
561-
#endif
562-
563-
#define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT
563+
#define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE
564564
#endif
565565

566566
//------------- CLASS -------------//

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