3535//--------------------------------------------------------------------+
3636// Callback weak stubs (called if application does not provide)
3737//--------------------------------------------------------------------+
38- TU_ATTR_WEAK void dcd_edpt0_status_complete (uint8_t rhport , tusb_control_request_t const * request ) {
39- (void )rhport ;
40- (void )request ;
38+ TU_ATTR_WEAK void dcd_edpt0_status_complete (uint8_t rhport , tusb_control_request_t const * request ) {
39+ (void ) rhport ;
40+ (void ) request ;
4141}
4242
4343//--------------------------------------------------------------------+
@@ -50,7 +50,7 @@ extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callb
5050
5151enum {
5252 EDPT_CTRL_OUT = 0x00 ,
53- EDPT_CTRL_IN = 0x80
53+ EDPT_CTRL_IN = 0x80
5454};
5555
5656typedef struct {
@@ -71,37 +71,34 @@ tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
7171//--------------------------------------------------------------------+
7272
7373// Queue ZLP status transaction
74- static inline bool _status_stage_xact (uint8_t rhport , tusb_control_request_t const * request )
75- {
74+ static inline bool _status_stage_xact (uint8_t rhport , tusb_control_request_t const * request ) {
7675 // Opposite to endpoint in Data Phase
7776 uint8_t const ep_addr = request -> bmRequestType_bit .direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN ;
7877 return usbd_edpt_xfer (rhport , ep_addr , NULL , 0 );
7978}
8079
8180// Status phase
82- bool tud_control_status (uint8_t rhport , tusb_control_request_t const * request )
83- {
84- _ctrl_xfer .request = (* request );
85- _ctrl_xfer .buffer = NULL ;
81+ bool tud_control_status (uint8_t rhport , tusb_control_request_t const * request ) {
82+ _ctrl_xfer .request = (* request );
83+ _ctrl_xfer .buffer = NULL ;
8684 _ctrl_xfer .total_xferred = 0 ;
87- _ctrl_xfer .data_len = 0 ;
85+ _ctrl_xfer .data_len = 0 ;
8886
8987 return _status_stage_xact (rhport , request );
9088}
9189
9290// Queue a transaction in Data Stage
9391// Each transaction has up to Endpoint0's max packet size.
9492// This function can also transfer an zero-length packet
95- static bool _data_stage_xact (uint8_t rhport )
96- {
97- uint16_t const xact_len = tu_min16 ( _ctrl_xfer . data_len - _ctrl_xfer . total_xferred , CFG_TUD_ENDPOINT0_SIZE );
93+ static bool _data_stage_xact (uint8_t rhport ) {
94+ uint16_t const xact_len = tu_min16 ( _ctrl_xfer . data_len - _ctrl_xfer . total_xferred ,
95+ CFG_TUD_ENDPOINT0_SIZE );
9896
9997 uint8_t ep_addr = EDPT_CTRL_OUT ;
10098
101- if ( _ctrl_xfer .request .bmRequestType_bit .direction == TUSB_DIR_IN )
102- {
99+ if (_ctrl_xfer .request .bmRequestType_bit .direction == TUSB_DIR_IN ) {
103100 ep_addr = EDPT_CTRL_IN ;
104- if ( xact_len ) {
101+ if (xact_len ) {
105102 TU_VERIFY (0 == tu_memcpy_s (_usbd_ctrl_buf , CFG_TUD_ENDPOINT0_SIZE , _ctrl_xfer .buffer , xact_len ));
106103 }
107104 }
@@ -111,29 +108,24 @@ static bool _data_stage_xact(uint8_t rhport)
111108
112109// Transmit data to/from the control endpoint.
113110// If the request's wLength is zero, a status packet is sent instead.
114- bool tud_control_xfer (uint8_t rhport , tusb_control_request_t const * request , void * buffer , uint16_t len )
115- {
116- _ctrl_xfer .request = (* request );
117- _ctrl_xfer .buffer = (uint8_t * ) buffer ;
111+ bool tud_control_xfer (uint8_t rhport , tusb_control_request_t const * request , void * buffer , uint16_t len ) {
112+ _ctrl_xfer .request = (* request );
113+ _ctrl_xfer .buffer = (uint8_t * ) buffer ;
118114 _ctrl_xfer .total_xferred = 0U ;
119- _ctrl_xfer .data_len = tu_min16 (len , request -> wLength );
115+ _ctrl_xfer .data_len = tu_min16 (len , request -> wLength );
120116
121- if (request -> wLength > 0U )
122- {
123- if (_ctrl_xfer .data_len > 0U )
124- {
117+ if (request -> wLength > 0U ) {
118+ if (_ctrl_xfer .data_len > 0U ) {
125119 TU_ASSERT (buffer );
126120 }
127121
128122// TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len);
129123
130124 // Data stage
131- TU_ASSERT ( _data_stage_xact (rhport ) );
132- }
133- else
134- {
125+ TU_ASSERT (_data_stage_xact (rhport ));
126+ } else {
135127 // Status stage
136- TU_ASSERT ( _status_stage_xact (rhport , request ) );
128+ TU_ASSERT (_status_stage_xact (rhport , request ));
137129 }
138130
139131 return true;
@@ -143,55 +135,49 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, vo
143135// USBD API
144136//--------------------------------------------------------------------+
145137void usbd_control_reset (void );
146- void usbd_control_set_request (tusb_control_request_t const * request );
147- void usbd_control_set_complete_callback ( usbd_control_xfer_cb_t fp );
148- bool usbd_control_xfer_cb (uint8_t rhport , uint8_t ep_addr , xfer_result_t event , uint32_t xferred_bytes );
138+ void usbd_control_set_request (tusb_control_request_t const * request );
139+ void usbd_control_set_complete_callback (usbd_control_xfer_cb_t fp );
140+ bool usbd_control_xfer_cb (uint8_t rhport , uint8_t ep_addr , xfer_result_t event , uint32_t xferred_bytes );
149141
150142void usbd_control_reset (void ) {
151143 tu_varclr (& _ctrl_xfer );
152144}
153145
154146// Set complete callback
155- void usbd_control_set_complete_callback ( usbd_control_xfer_cb_t fp )
156- {
147+ void usbd_control_set_complete_callback (usbd_control_xfer_cb_t fp ) {
157148 _ctrl_xfer .complete_cb = fp ;
158149}
159150
160151// for dcd_set_address where DCD is responsible for status response
161- void usbd_control_set_request (tusb_control_request_t const * request )
162- {
163- _ctrl_xfer .request = (* request );
164- _ctrl_xfer .buffer = NULL ;
152+ void usbd_control_set_request (tusb_control_request_t const * request ) {
153+ _ctrl_xfer .request = (* request );
154+ _ctrl_xfer .buffer = NULL ;
165155 _ctrl_xfer .total_xferred = 0 ;
166- _ctrl_xfer .data_len = 0 ;
156+ _ctrl_xfer .data_len = 0 ;
167157}
168158
169159// callback when a transaction complete on
170160// - DATA stage of control endpoint or
171161// - Status stage
172- bool usbd_control_xfer_cb (uint8_t rhport , uint8_t ep_addr , xfer_result_t result , uint32_t xferred_bytes )
173- {
162+ bool usbd_control_xfer_cb (uint8_t rhport , uint8_t ep_addr , xfer_result_t result , uint32_t xferred_bytes ) {
174163 (void ) result ;
175164
176165 // Endpoint Address is opposite to direction bit, this is Status Stage complete event
177- if ( tu_edpt_dir (ep_addr ) != _ctrl_xfer .request .bmRequestType_bit .direction )
178- {
166+ if (tu_edpt_dir (ep_addr ) != _ctrl_xfer .request .bmRequestType_bit .direction ) {
179167 TU_ASSERT (0 == xferred_bytes );
180168
181169 // invoke optional dcd hook if available
182170 dcd_edpt0_status_complete (rhport , & _ctrl_xfer .request );
183171
184- if (_ctrl_xfer .complete_cb )
185- {
172+ if (_ctrl_xfer .complete_cb ) {
186173 // TODO refactor with usbd_driver_print_control_complete_name
187174 _ctrl_xfer .complete_cb (rhport , CONTROL_STAGE_ACK , & _ctrl_xfer .request );
188175 }
189176
190177 return true;
191178 }
192179
193- if ( _ctrl_xfer .request .bmRequestType_bit .direction == TUSB_DIR_OUT )
194- {
180+ if (_ctrl_xfer .request .bmRequestType_bit .direction == TUSB_DIR_OUT ) {
195181 TU_VERIFY (_ctrl_xfer .buffer );
196182 memcpy (_ctrl_xfer .buffer , _usbd_ctrl_buf , xferred_bytes );
197183 TU_LOG_MEM (CFG_TUD_LOG_LEVEL , _usbd_ctrl_buf , xferred_bytes , 2 );
@@ -202,37 +188,32 @@ bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result
202188
203189 // Data Stage is complete when all request's length are transferred or
204190 // a short packet is sent including zero-length packet.
205- if ( (_ctrl_xfer .request .wLength == _ctrl_xfer .total_xferred ) || ( xferred_bytes < CFG_TUD_ENDPOINT0_SIZE ) )
206- {
191+ if ((_ctrl_xfer .request .wLength == _ctrl_xfer .total_xferred ) ||
192+ ( xferred_bytes < CFG_TUD_ENDPOINT0_SIZE )) {
207193 // DATA stage is complete
208194 bool is_ok = true;
209195
210196 // invoke complete callback if set
211197 // callback can still stall control in status phase e.g out data does not make sense
212- if ( _ctrl_xfer .complete_cb )
213- {
198+ if (_ctrl_xfer .complete_cb ) {
214199 #if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
215200 usbd_driver_print_control_complete_name (_ctrl_xfer .complete_cb );
216201 #endif
217202
218203 is_ok = _ctrl_xfer .complete_cb (rhport , CONTROL_STAGE_DATA , & _ctrl_xfer .request );
219204 }
220205
221- if ( is_ok )
222- {
206+ if (is_ok ) {
223207 // Send status
224- TU_ASSERT ( _status_stage_xact (rhport , & _ctrl_xfer .request ) );
225- }else
226- {
208+ TU_ASSERT (_status_stage_xact (rhport , & _ctrl_xfer .request ));
209+ } else {
227210 // Stall both IN and OUT control endpoint
228211 dcd_edpt_stall (rhport , EDPT_CTRL_OUT );
229212 dcd_edpt_stall (rhport , EDPT_CTRL_IN );
230213 }
231- }
232- else
233- {
214+ } else {
234215 // More data to transfer
235- TU_ASSERT ( _data_stage_xact (rhport ) );
216+ TU_ASSERT (_data_stage_xact (rhport ));
236217 }
237218
238219 return true;
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