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hathachhathach
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Merge pull request #3220 from adam-embedded/with-stm32l496nucleo
Added stm32l496nucleo board support
2 parents 2e29d1c + 10e86b0 commit 97741a5

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‎hw/bsp/stm32l4/boards/stm32l496nucleo/STM32L496ZGTX_FLASH.ld‎

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/*
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******************************************************************************
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**
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** @file : LinkerScript.ld
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**
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** @author : Auto-generated by STM32CubeIDE
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**
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** Abstract : Linker script for NUCLEO-L496ZG Board embedding STM32L496ZGTx Device from stm32l4 series
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** 1024Kbytes ROM
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** 256Kbytes RAM
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** 64Kbytes SRAM2
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**
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** Set heap size, stack size and stack location according
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** to application requirements.
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**
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** Set memory bank area and size if external memory is used
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**
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** Target : STMicroelectronics STM32
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**
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** Distribution: The file is distributed as is, without any warranty
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** of any kind.
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**
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******************************************************************************
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** @attention
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**
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** Copyright (c) 2022 STMicroelectronics.
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** All rights reserved.
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**
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** This software is licensed under terms that can be found in the LICENSE file
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** in the root directory of this software component.
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** If no LICENSE file comes with this software, it is provided AS-IS.
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**
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******************************************************************************
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*/
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/* Entry Point */
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ENTRY(Reset_Handler)
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_Min_Heap_Size = 0x200; /* required amount of heap */
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_Min_Stack_Size = 0x400; /* required amount of stack */
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/* Memories definition */
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MEMORY
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{
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RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 256K
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SRAM2 (xrw) : ORIGIN = 0x10000000, LENGTH = 64K
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ROM (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
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}
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/* Highest address of the user mode stack */
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_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
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/* Sections */
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SECTIONS
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{
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/* The startup code into "ROM" Rom type memory */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector)) /* Startup code */
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. = ALIGN(4);
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} >ROM
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/* The program code and other data into "ROM" Rom type memory */
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.text :
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{
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. = ALIGN(4);
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*(.text) /* .text sections (code) */
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*(.text*) /* .text* sections (code) */
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*(.glue_7) /* glue arm to thumb code */
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*(.glue_7t) /* glue thumb to arm code */
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*(.eh_frame)
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KEEP (*(.init))
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KEEP (*(.fini))
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. = ALIGN(4);
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_etext = .; /* define a global symbols at end of code */
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} >ROM
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/* Constant data into "ROM" Rom type memory */
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.rodata :
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{
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. = ALIGN(4);
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*(.rodata) /* .rodata sections (constants, strings, etc.) */
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*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
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. = ALIGN(4);
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} >ROM
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.ARM.extab :
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{
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} >ROM
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.ARM :
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{
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. = ALIGN(4);
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__exidx_start = .;
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*(.ARM.exidx*)
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__exidx_end = .;
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. = ALIGN(4);
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} >ROM
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.preinit_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP (*(.preinit_array*))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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} >ROM
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.init_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP (*(SORT(.init_array.*)))
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KEEP (*(.init_array*))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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} >ROM
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.fini_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP (*(SORT(.fini_array.*)))
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KEEP (*(.fini_array*))
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PROVIDE_HIDDEN (__fini_array_end = .);
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. = ALIGN(4);
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} >ROM
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/* Used by the startup to initialize data */
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_sidata = LOADADDR(.data);
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/* Initialized data sections into "RAM" Ram type memory */
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.data :
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{
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. = ALIGN(4);
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_sdata = .; /* create a global symbol at data start */
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*(.data) /* .data sections */
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*(.data*) /* .data* sections */
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*(.RamFunc) /* .RamFunc sections */
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*(.RamFunc*) /* .RamFunc* sections */
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. = ALIGN(4);
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_edata = .; /* define a global symbol at data end */
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} >RAM AT> ROM
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_sisram2 = LOADADDR(.sram2);
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/* SRAM2 section
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*
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* IMPORTANT NOTE!
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* If initialized variables will be placed in this section,
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* the startup code needs to be modified to copy the init-values.
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*/
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.sram2 :
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{
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. = ALIGN(4);
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_ssram2 = .; /* create a global symbol at sram2 start */
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*(.sram2)
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*(.sram2*)
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. = ALIGN(4);
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_esram2 = .; /* create a global symbol at sram2 end */
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} >SRAM2 AT> ROM
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/* Uninitialized data section into "RAM" Ram type memory */
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. = ALIGN(4);
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.bss :
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{
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/* This is used by the startup in order to initialize the .bss section */
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_sbss = .; /* define a global symbol at bss start */
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .; /* define a global symbol at bss end */
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__bss_end__ = _ebss;
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} >RAM
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/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
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._user_heap_stack :
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{
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. = ALIGN(8);
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PROVIDE ( end = . );
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PROVIDE ( _end = . );
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. = . + _Min_Heap_Size;
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} >RAM
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/* Remove information from the compiler libraries */
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/DISCARD/ :
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{
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libc.a ( * )
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libm.a ( * )
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libgcc.a ( * )
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}
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.ARM.attributes 0 : { *(.ARM.attributes) }
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}

‎hw/bsp/stm32l4/boards/stm32l496nucleo/board.cmake‎

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set(MCU_VARIANT stm32l496xx)
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set(JLINK_DEVICE stm32l496zg)
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set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L496ZGTX_FLASH.ld)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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STM32L496xx
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)
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endfunction()

‎hw/bsp/stm32l4/boards/stm32l496nucleo/board.h‎

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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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/* metadata:
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name: STM32 L496 Nucleo
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url: https://www.st.com/en/evaluation-tools/nucleo-l496ZG-P.html
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LED_PORT GPIOB
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#define LED_PIN GPIO_PIN_7
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#define LED_STATE_ON 1
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// Not a real button
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#define BUTTON_PORT GPIOC
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#define BUTTON_PIN GPIO_PIN_13
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#define BUTTON_STATE_ACTIVE 1
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#define UART_DEV LPUART1
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#define UART_CLK_EN __HAL_RCC_LPUART1_CLK_ENABLE
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#define UART_GPIO_PORT GPIOG
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#define UART_GPIO_AF GPIO_AF8_LPUART1
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#define UART_TX_PIN GPIO_PIN_7
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#define UART_RX_PIN GPIO_PIN_8
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//--------------------------------------------------------------------+
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// RCC Clock
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//--------------------------------------------------------------------+
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (MSI)
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* SYSCLK(Hz) = 80000000
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* HCLK(Hz) = 80000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 1
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* APB2 Prescaler = 1
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* MSI Frequency(Hz) = 8000000
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* PLL_M = 1
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* PLL_N = 10
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* PLL_Q = 2
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* PLL_R = 2
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* VDD(V) = 3.3
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* @param None
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* @retval None
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*/
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static inline void board_clock_init(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Configure LSE Drive Capability
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*/
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HAL_PWR_EnableBkUpAccess();
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__HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = 1;
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RCC_OscInitStruct.PLL.PLLN = 10;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4);
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// /** Enable the SYSCFG APB clock
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// */
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// __HAL_RCC_CRS_CLK_ENABLE();
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//
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// /** Configures CRS
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// */
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// RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
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// RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
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// RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
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// RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
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// RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
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// RCC_CRSInitStruct.ErrorLimitValue = 34;
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// RCC_CRSInitStruct.HSI48CalibrationValue = 32;
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//
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// HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
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/* Select HSI48 output as USB clock source */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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/* Select PLL output as UART clock source */
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PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
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PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
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HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
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}
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static inline void board_vbus_sense_init(void)
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{
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// Enable VBUS sense (B device) via pin PA9
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USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H_ */

‎hw/bsp/stm32l4/boards/stm32l496nucleo/board.mk‎

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CFLAGS += \
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-DSTM32L496xx \
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# GCC
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SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32l496xx.s
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LD_FILE_GCC = $(BOARD_PATH)/STM32L496ZGTX_FLASH.ld
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# IAR
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SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32l496xx.s
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LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32l496xx_flash.icf
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# For flash-jlink target
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JLINK_DEVICE = stm32l496zg

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