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hathachhathach
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add ra6m1 board
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11 files changed

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‎hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h‎

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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
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#define BSP_FEATURE_TFU_SUPPORTED 0
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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// for SystemInit()
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void bsp_init(void * p_args);

‎hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h‎

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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)

‎hw/bsp/ra/boards/ra6m1_ek/board.h‎

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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2023 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define LED1 BSP_IO_PORT_01_PIN_12
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#define LED_STATE_ON 1
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#define SW1 BSP_IO_PORT_04_PIN_15
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#define BUTTON_STATE_ACTIVE 0
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const ioport_pin_cfg_t board_pin_cfg[] = {
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{.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
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{.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
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// USB D+, D-, VBus
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{.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
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{.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
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{.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef BSP_CFG_H_
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#define BSP_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_clock_cfg.h"
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#include "bsp_mcu_family_cfg.h"
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#define RA_NOT_DEFINED 0
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#ifndef BSP_CFG_RTOS
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#if (RA_NOT_DEFINED) != (2)
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#define BSP_CFG_RTOS (2)
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#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
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#define BSP_CFG_RTOS (1)
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#else
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#define BSP_CFG_RTOS (0)
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#endif
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#endif
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#ifndef BSP_CFG_RTC_USED
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#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
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#endif
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#undef RA_NOT_DEFINED
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#if defined(_RA_BOOT_IMAGE)
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#define BSP_CFG_BOOT_IMAGE (1)
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#endif
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#define BSP_CFG_MCU_VCC_MV (3300)
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#define BSP_CFG_STACK_MAIN_BYTES (0x400)
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#define BSP_CFG_HEAP_BYTES (0x1000)
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#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
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#define BSP_CFG_ASSERT (0)
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#define BSP_CFG_ERROR_LOG (0)
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#define BSP_CFG_PFS_PROTECT ((1))
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#define BSP_CFG_C_RUNTIME_INIT ((1))
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#define BSP_CFG_EARLY_INIT ((0))
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#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
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#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
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#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
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#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
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#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
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#endif
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#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
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#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
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#endif
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#define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK 0
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#define BSP_FEATURE_TFU_SUPPORTED 0
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#define BSP_TZ_SECURE_BUILD (0)
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#define BSP_TZ_NONSECURE_BUILD (0)
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#define BSP_CFG_USE_LOW_VOLTAGE_MODE 0
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// for SystemInit()
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void bsp_init(void * p_args);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_CFG_H_ */

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_clock_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef BSP_CLOCK_CFG_H_
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#define BSP_CLOCK_CFG_H_
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#define BSP_CFG_CLOCKS_SECURE (0)
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#define BSP_CFG_CLOCKS_OVERRIDE (0)
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#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */
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#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
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#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
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#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */
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#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */
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#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
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#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
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#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
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#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
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#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
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#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
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#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
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#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
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#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
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#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
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#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
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#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
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#endif /* BSP_CLOCK_CFG_H_ */

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_CFG_H_
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#define BSP_MCU_DEVICE_CFG_H_
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#define BSP_CFG_MCU_PART_SERIES (6)
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#endif /* BSP_MCU_DEVICE_CFG_H_ */

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_DEVICE_PN_CFG_H_
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#define BSP_MCU_R7FA6M1AD3CFP
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#define BSP_MCU_FEATURE_SET ('A')
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#define BSP_ROM_SIZE_BYTES (524288)
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#define BSP_RAM_SIZE_BYTES (262144)
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#define BSP_DATA_FLASH_SIZE_BYTES (8192)
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#define BSP_PACKAGE_LQFP
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#define BSP_PACKAGE_PINS (100)
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#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef BSP_MCU_FAMILY_CFG_H_
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#define BSP_MCU_FAMILY_CFG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "bsp_mcu_device_pn_cfg.h"
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#include "bsp_mcu_device_cfg.h"
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#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
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#include "bsp_clock_cfg.h"
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#define BSP_MCU_GROUP_RA6M1 (1)
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#define BSP_LOCO_HZ (32768)
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#define BSP_MOCO_HZ (8000000)
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#define BSP_SUB_CLOCK_HZ (32768)
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#if BSP_CFG_HOCO_FREQUENCY == 0
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#define BSP_HOCO_HZ (16000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 1
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#define BSP_HOCO_HZ (18000000)
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#elif BSP_CFG_HOCO_FREQUENCY == 2
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#define BSP_HOCO_HZ (20000000)
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#else
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#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
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#endif
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#define BSP_CFG_FLL_ENABLE (0)
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#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
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#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
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#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
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#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
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#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
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#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
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#define OFS_SEQ5 (1 << 28) | (1 << 30)
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#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
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#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
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#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
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#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
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#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
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#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
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#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
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#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
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#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
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#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
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#endif
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/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
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#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
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/*
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ID Code
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Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
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WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
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*/
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#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
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#define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
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#define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
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#else
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/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
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#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
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#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* BSP_MCU_FAMILY_CFG_H_ */

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_pin_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef BSP_PIN_CFG_H_
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#define BSP_PIN_CFG_H_
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#include "r_ioport.h"
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/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
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FSP_HEADER
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extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
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void BSP_PinConfigSecurityInit();
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/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
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FSP_FOOTER
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#endif /* BSP_PIN_CFG_H_ */

‎hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/r_ioport_cfg.h‎

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/* generated configuration header file - do not edit */
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#ifndef R_IOPORT_CFG_H_
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#define R_IOPORT_CFG_H_
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#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
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#endif /* R_IOPORT_CFG_H_ */

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