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hathachhathach
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clean up
1 parent b67e008 commit e0f2343

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3 files changed

+124
-146
lines changed

3 files changed

+124
-146
lines changed

‎src/portable/st/stm32_fsdev/fsdev_at32.h‎

Lines changed: 72 additions & 76 deletions
Original file line numberDiff line numberDiff line change
@@ -35,82 +35,6 @@
3535

3636
#endif
3737

38-
//#include "fsdev_common.h"
39-
40-
//--------------------------------------------------------------------+
41-
//
42-
//--------------------------------------------------------------------+
43-
44-
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
45-
static const IRQn_Type fsdev_irq[] = {
46-
USBFS_H_CAN1_TX_IRQn,
47-
USBFS_L_CAN1_RX0_IRQn,
48-
USBFSWakeUp_IRQn
49-
};
50-
enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
51-
52-
#else
53-
#error "Unsupported MCU"
54-
#endif
55-
56-
void dcd_int_enable(uint8_t rhport) {
57-
(void)rhport;
58-
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
59-
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
60-
// shared USB/CAN IRQs to separate CAN and USB IRQs.
61-
// This dynamically checks if this remap is active to enable the right IRQs.
62-
if (CRM->intmap_bit.usbintmap) {
63-
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
64-
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
65-
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
66-
} else
67-
#endif
68-
{
69-
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
70-
NVIC_EnableIRQ(fsdev_irq[i]);
71-
}
72-
}
73-
}
74-
75-
void dcd_int_disable(uint8_t rhport) {
76-
(void)rhport;
77-
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
78-
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
79-
// shared USB/CAN IRQs to separate CAN and USB IRQs.
80-
// This dynamically checks if this remap is active to enable the right IRQs.
81-
if (CRM->intmap_bit.usbintmap) {
82-
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
83-
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
84-
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
85-
} else
86-
#endif
87-
{
88-
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
89-
NVIC_DisableIRQ(fsdev_irq[i]);
90-
}
91-
}
92-
}
93-
94-
void dcd_disconnect(uint8_t rhport) {
95-
(void) rhport;
96-
/* disable usb phy */
97-
//USB->ctrl_bit.disusb = TRUE;
98-
*(int *)(0x40000000+0x5C00+0x40) |= (1<<1);
99-
*(int *)(0x40000000+0x5C00+0x60) |= (1<<1);
100-
/* D+ 1.5k pull-up disable */
101-
//USB->cfg_bit.puo = TRUE;
102-
}
103-
104-
void dcd_connect(uint8_t rhport) {
105-
(void) rhport;
106-
/* enable usb phy */
107-
//USB->ctrl_bit.disusb = 0;
108-
*(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1);
109-
*(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1);
110-
/* Dp 1.5k pull-up enable */
111-
//USB->cfg_bit.puo = 0;
112-
}
113-
11438
#define FSDEV_PMA_SIZE (512u)
11539
#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
11640
#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
@@ -221,4 +145,76 @@ void dcd_connect(uint8_t rhport) {
221145
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
222146
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
223147

148+
#include "fsdev_type.h"
149+
150+
//--------------------------------------------------------------------+
151+
//
152+
//--------------------------------------------------------------------+
153+
154+
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
155+
static const IRQn_Type fsdev_irq[] = {
156+
USBFS_H_CAN1_TX_IRQn,
157+
USBFS_L_CAN1_RX0_IRQn,
158+
USBFSWakeUp_IRQn
159+
};
160+
enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
161+
162+
#else
163+
#error "Unsupported MCU"
164+
#endif
165+
166+
void dcd_int_enable(uint8_t rhport) {
167+
(void)rhport;
168+
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
169+
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
170+
// shared USB/CAN IRQs to separate CAN and USB IRQs.
171+
// This dynamically checks if this remap is active to enable the right IRQs.
172+
if (CRM->intmap_bit.usbintmap) {
173+
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
174+
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
175+
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
176+
} else
177+
#endif
178+
{
179+
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
180+
NVIC_EnableIRQ(fsdev_irq[i]);
181+
}
182+
}
183+
}
184+
185+
void dcd_int_disable(uint8_t rhport) {
186+
(void)rhport;
187+
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
188+
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
189+
// shared USB/CAN IRQs to separate CAN and USB IRQs.
190+
// This dynamically checks if this remap is active to enable the right IRQs.
191+
if (CRM->intmap_bit.usbintmap) {
192+
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
193+
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
194+
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
195+
} else
196+
#endif
197+
{
198+
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
199+
NVIC_DisableIRQ(fsdev_irq[i]);
200+
}
201+
}
202+
}
203+
204+
void dcd_disconnect(uint8_t rhport) {
205+
(void) rhport;
206+
/* disable usb phy */
207+
FSDEV_REG->CNTR |= USB_CNTR_PDWN;
208+
/* D+ 1.5k pull-up disable, USB->cfg_bit.puo = TRUE; */
209+
*(uint32_t *)(FSDEV_REG_BASE+0x60) |= (1u<<1);
210+
}
211+
212+
void dcd_connect(uint8_t rhport) {
213+
(void) rhport;
214+
/* enable usb phy */
215+
FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
216+
/* Dp 1.5k pull-up enable, USB->cfg_bit.puo = 0; */
217+
*(uint32_t *)(FSDEV_REG_BASE+0x60) &= ~(1u<<1);
218+
}
219+
224220
#endif

‎src/portable/synopsys/dwc2/dwc2_at32.h‎

Lines changed: 46 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -67,66 +67,52 @@
6767
extern "C" {
6868
#endif
6969

70-
static const dwc2_controller_t _dwc2_controller[] =
71-
{
72-
{ .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE },
73-
#if defined DWC2_OTG2_REG_BASE
74-
{ .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE }
75-
#endif
76-
};
77-
78-
TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
79-
(void) role;
80-
const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
81-
if (enabled) {
82-
NVIC_EnableIRQ(irqn);
83-
} else {
84-
NVIC_DisableIRQ(irqn);
85-
}
86-
}
87-
88-
TU_ATTR_ALWAYS_INLINE
89-
static inline void dwc2_dcd_int_enable(uint8_t rhport)
90-
{
91-
NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
92-
}
93-
94-
TU_ATTR_ALWAYS_INLINE
95-
static inline void dwc2_dcd_int_disable (uint8_t rhport)
96-
{
97-
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
98-
}
99-
100-
static inline void dwc2_remote_wakeup_delay(void)
101-
{
102-
// try to delay for 1 ms
103-
uint32_t count = system_core_clock / 1000;
104-
while ( count-- ) __asm volatile ("nop");
105-
}
106-
107-
// MCU specific PHY init, called BEFORE core reset
108-
static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
109-
{
110-
(void) dwc2;
111-
// Enable on-chip HS PHY
112-
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI)
113-
{
114-
115-
}
116-
else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED)
117-
{
118-
119-
}
120-
}
121-
122-
// MCU specific PHY update, it is called AFTER init() and core reset
123-
static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
124-
{
125-
(void) dwc2;
126-
(void) hs_phy_type;
127-
128-
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
129-
}
70+
static const dwc2_controller_t _dwc2_controller[] = {
71+
{.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE},
72+
#if defined DWC2_OTG2_REG_BASE
73+
{.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE}
74+
#endif
75+
};
76+
77+
TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
78+
(void) role;
79+
const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
80+
if (enabled) {
81+
NVIC_EnableIRQ(irqn);
82+
} else {
83+
NVIC_DisableIRQ(irqn);
84+
}
85+
}
86+
87+
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
88+
}
89+
90+
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
91+
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
92+
}
93+
94+
TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
95+
// try to delay for 1 ms
96+
uint32_t count = system_core_clock / 1000;
97+
while (count--) __asm volatile("nop");
98+
}
99+
100+
// MCU specific PHY init, called BEFORE core reset
101+
TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
102+
(void) dwc2;
103+
// Enable on-chip HS PHY
104+
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
105+
} else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
106+
}
107+
}
108+
109+
// MCU specific PHY update, it is called AFTER init() and core reset
110+
TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
111+
(void) dwc2;
112+
(void) hs_phy_type;
113+
114+
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
115+
}
130116

131117
#ifdef __cplusplus
132118
}

‎src/portable/synopsys/dwc2/dwc2_common.c‎

Lines changed: 6 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -120,13 +120,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
120120

121121
// Set 16-bit interface if supported
122122
if (ghwcfg4.phy_data_width) {
123+
#if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
123124
gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
124-
125-
/* at32f402_405 does not actually support 16-bit */
126-
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
127-
gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
128125
#endif
129-
130126
} else {
131127
gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
132128
}
@@ -145,12 +141,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
145141
// - 9 if using 8-bit PHY interface
146142
// - 5 if using 16-bit PHY interface
147143
gusbcfg &= ~GUSBCFG_TRDT_Msk;
148-
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
149144

150-
/* at32f402_405 does not actually support 16-bit */
151-
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
152-
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos;
153-
#endif
145+
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
146+
gusbcfg |= 9u << GUSBCFG_TRDT_Pos;
147+
#else
148+
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
149+
#endif
154150

155151
dwc2->gusbcfg = gusbcfg;
156152

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