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hathachhathach
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Merge pull request #3137 from HiFiPhile/uac_simplify
uac2: remove support fifo
2 parents 99b4ebe + dc0038f commit e95973d

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8 files changed

+119
-1157
lines changed

8 files changed

+119
-1157
lines changed

‎examples/device/audio_4_channel_mic/src/main.c‎

Lines changed: 0 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -69,13 +69,8 @@ uint8_t clkValid;
6969
audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state
7070
audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state
7171

72-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
73-
// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
74-
uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
75-
#else
7672
// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
7773
uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000];
78-
#endif
7974

8075
void led_blinking_task(void);
8176
void audio_task(void);
@@ -106,27 +101,6 @@ int main(void)
106101
sampleFreqRng.subrange[0].bRes = 0;
107102

108103
// Generate dummy data
109-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
110-
uint16_t * p_buff = i2s_dummy_buffer[0];
111-
uint16_t dataVal = 0;
112-
for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
113-
{
114-
// CH0 saw wave
115-
*p_buff++ = dataVal;
116-
// CH1 inverted saw wave
117-
*p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
118-
dataVal+= 32;
119-
}
120-
p_buff = i2s_dummy_buffer[1];
121-
for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
122-
{
123-
// CH3 square wave
124-
*p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
125-
// CH4 sinus wave
126-
float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
127-
*p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
128-
}
129-
#else
130104
uint16_t * p_buff = i2s_dummy_buffer;
131105
uint16_t dataVal = 0;
132106
for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
@@ -142,7 +116,6 @@ int main(void)
142116
float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
143117
*p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
144118
}
145-
#endif
146119

147120
while (1)
148121
{
@@ -195,15 +168,7 @@ void audio_task(void)
195168
uint32_t curr_ms = board_millis();
196169
if ( start_ms == curr_ms ) return; // not enough time
197170
start_ms = curr_ms;
198-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
199-
// Write I2S buffer into FIFO
200-
for (uint8_t cnt=0; cnt < 2; cnt++)
201-
{
202-
tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
203-
}
204-
#else
205171
tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
206-
#endif
207172
}
208173

209174
//--------------------------------------------------------------------+

‎examples/device/audio_4_channel_mic/src/tusb_config.h‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -115,26 +115,11 @@ extern "C" {
115115
#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
116116
#define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
117117

118-
#define CFG_TUD_AUDIO_ENABLE_ENCODING 1
119118
#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1
120119

121-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
122-
123-
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
124-
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN
125-
126-
#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1
127-
#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
128-
#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
129-
#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device
130-
131-
#else
132-
133120
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
134121
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
135122

136-
#endif
137-
138123
#ifdef __cplusplus
139124
}
140125
#endif

‎examples/device/audio_4_channel_mic_freertos/src/main.c‎

Lines changed: 0 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -105,13 +105,8 @@ uint8_t clkValid;
105105
audio_control_range_2_n_t(1) volumeRng[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX+1]; // Volume range state
106106
audio_control_range_4_n_t(1) sampleFreqRng; // Sample frequency range state
107107

108-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
109-
// Audio test data, each buffer contains 2 channels, buffer[0] for CH0-1, buffer[1] for CH1-2
110-
uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO][CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000/CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO];
111-
#else
112108
// Audio test data, 4 channels muxed together, buffer[0] for CH0, buffer[1] for CH1, buffer[2] for CH2, buffer[3] for CH3
113109
uint16_t i2s_dummy_buffer[CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX*CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE/1000];
114-
#endif
115110

116111
void led_blinking_task(void* param);
117112
void usb_device_task(void* param);
@@ -132,27 +127,6 @@ int main(void)
132127
sampleFreqRng.subrange[0].bRes = 0;
133128

134129
// Generate dummy data
135-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
136-
uint16_t * p_buff = i2s_dummy_buffer[0];
137-
uint16_t dataVal = 0;
138-
for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
139-
{
140-
// CH0 saw wave
141-
*p_buff++ = dataVal;
142-
// CH1 inverted saw wave
143-
*p_buff++ = 3200 + AUDIO_SAMPLE_RATE/1000 - dataVal;
144-
dataVal+= 32;
145-
}
146-
p_buff = i2s_dummy_buffer[1];
147-
for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
148-
{
149-
// CH3 square wave
150-
*p_buff++ = cnt < (AUDIO_SAMPLE_RATE/1000/2) ? 3400:5000;
151-
// CH4 sinus wave
152-
float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
153-
*p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
154-
}
155-
#else
156130
uint16_t * p_buff = i2s_dummy_buffer;
157131
uint16_t dataVal = 0;
158132
for (uint16_t cnt = 0; cnt < AUDIO_SAMPLE_RATE/1000; cnt++)
@@ -168,7 +142,6 @@ int main(void)
168142
float t = 2*3.1415f * cnt / (AUDIO_SAMPLE_RATE/1000);
169143
*p_buff++ = (uint16_t)((int16_t)(sinf(t) * 750) + 6000);
170144
}
171-
#endif
172145

173146
#if configSUPPORT_STATIC_ALLOCATION
174147
// blinky task
@@ -269,15 +242,7 @@ void audio_task(void* param)
269242
// Here we simulate a I2S receive callback every 1ms.
270243
while (1) {
271244
vTaskDelay(1);
272-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
273-
// Write I2S buffer into FIFO
274-
for (uint8_t cnt=0; cnt < 2; cnt++)
275-
{
276-
tud_audio_write_support_ff(cnt, i2s_dummy_buffer[cnt], AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX);
277-
}
278-
#else
279245
tud_audio_write(i2s_dummy_buffer, AUDIO_SAMPLE_RATE/1000 * CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX * CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX);
280-
#endif
281246
}
282247
}
283248

‎examples/device/audio_4_channel_mic_freertos/src/tusb_config.h‎

Lines changed: 0 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -121,26 +121,11 @@ extern "C" {
121121
#define CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX 4 // This value is not required by the driver, it parses this information from the descriptor once the alternate interface is set by the host - we use it for the setup
122122
#define CFG_TUD_AUDIO_EP_SZ_IN TUD_AUDIO_EP_SIZE(CFG_TUD_AUDIO_FUNC_1_SAMPLE_RATE, CFG_TUD_AUDIO_FUNC_1_N_BYTES_PER_SAMPLE_TX, CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX)
123123

124-
#define CFG_TUD_AUDIO_ENABLE_ENCODING 1
125124
#define CFG_TUD_AUDIO_EP_IN_FLOW_CONTROL 1
126125

127-
#if CFG_TUD_AUDIO_ENABLE_ENCODING
128-
129-
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
130-
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ CFG_TUD_AUDIO_EP_SZ_IN
131-
132-
#define CFG_TUD_AUDIO_ENABLE_TYPE_I_ENCODING 1
133-
#define CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX 2 // One I2S stream contains two channels, each stream is saved within one support FIFO - this value is currently fixed, the driver does not support a changing value
134-
#define CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO (CFG_TUD_AUDIO_FUNC_1_N_CHANNELS_TX / CFG_TUD_AUDIO_FUNC_1_CHANNEL_PER_FIFO_TX)
135-
#define CFG_TUD_AUDIO_FUNC_1_TX_SUPP_SW_FIFO_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * (CFG_TUD_AUDIO_EP_SZ_IN / CFG_TUD_AUDIO_FUNC_1_N_TX_SUPP_SW_FIFO) // Example write FIFO every 1ms, so it should be 8 times larger for HS device
136-
137-
#else
138-
139126
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SZ_MAX CFG_TUD_AUDIO_EP_SZ_IN
140127
#define CFG_TUD_AUDIO_FUNC_1_EP_IN_SW_BUF_SZ (TUD_OPT_HIGH_SPEED ? 32 : 4) * CFG_TUD_AUDIO_EP_SZ_IN // Example write FIFO every 1ms, so it should be 8 times larger for HS device
141128

142-
#endif
143-
144129
#ifdef __cplusplus
145130
}
146131
#endif

‎hw/bsp/stm32c0/boards/stm32c071nucleo/board.h‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,9 +55,45 @@
5555

5656
// Enable UART serial communication with the ST-Link
5757
#define UART_DEV USART2
58+
#define UART_CLK_EN __HAL_RCC_USART2_CLK_ENABLE
5859
#define UART_GPIO_PORT GPIOA
5960
#define UART_GPIO_AF GPIO_AF1_USART2
6061
#define UART_TX_PIN GPIO_PIN_2
6162
#define UART_RX_PIN GPIO_PIN_3
6263

64+
static inline void board_clock_init(void) {
65+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
66+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
67+
RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
68+
69+
/* -1- Enable HSIUSB48 Oscillator */
70+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
71+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
72+
73+
HAL_RCC_OscConfig(&RCC_OscInitStruct);
74+
75+
/* -2- Initializes the CPU, AHB and APB buses clocks */
76+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
77+
|RCC_CLOCKTYPE_PCLK1;
78+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSIUSB48;
79+
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
80+
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
81+
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
82+
83+
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
84+
85+
86+
__HAL_RCC_CRS_CLK_ENABLE();
87+
88+
// Configures CRS
89+
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
90+
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
91+
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
92+
RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000,1000);
93+
RCC_CRSInitStruct.ErrorLimitValue = 34;
94+
RCC_CRSInitStruct.HSI48CalibrationValue = 32;
95+
96+
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
97+
}
98+
6399
#endif /* BOARD_H_ */

‎hw/bsp/stm32c0/family.c‎

Lines changed: 9 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -53,31 +53,16 @@ UART_HandleTypeDef UartHandle;
5353

5454
void board_init(void) {
5555
HAL_Init();
56-
57-
// Enable the HSIUSB48 48 MHz oscillator.
58-
RCC->CR |= RCC_CR_HSIUSB48ON;
59-
60-
// Wait for HSIUSB48 to be ready.
61-
while (!(RCC->CR & RCC_CR_HSIUSB48RDY)) { }
62-
63-
// Change the SYSCLK source to HSIUSB48.
64-
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_SYSCLKSOURCE_HSIUSB48;
65-
66-
// Wait for the SYSCLK source to change.
67-
while ((RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos != RCC_SYSCLKSOURCE_HSIUSB48) { }
68-
69-
// Disable HSI48 to save power.
70-
RCC->CR &= ~RCC_CR_HSION;
56+
board_clock_init();
7157

7258
// Enable peripheral clocks.
73-
RCC->APBENR1 = RCC_APBENR1_USBEN | RCC_APBENR1_CRSEN | RCC_APBENR1_USART2EN;
74-
RCC->APBENR2 = RCC_APBENR2_USART1EN;
75-
76-
// Enable all GPIO clocks.
77-
RCC->IOPENR = 0x2F;
78-
79-
// Turn on CRS to make the HSIUSB48 clock more precise when USB is connected.
80-
CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
59+
__HAL_RCC_USB_CLK_ENABLE();
60+
__HAL_RCC_GPIOA_CLK_ENABLE();
61+
__HAL_RCC_GPIOB_CLK_ENABLE();
62+
__HAL_RCC_GPIOC_CLK_ENABLE();
63+
__HAL_RCC_GPIOD_CLK_ENABLE();
64+
__HAL_RCC_SYSCFG_CLK_ENABLE();
65+
__HAL_RCC_PWR_CLK_ENABLE();
8166

8267
#if CFG_TUSB_OS == OPT_OS_NONE
8368
// 1ms tick timer
@@ -109,6 +94,7 @@ void board_init(void) {
10994
}
11095

11196
#ifdef UART_DEV
97+
UART_CLK_EN();
11298
// UART
11399
{
114100
GPIO_InitTypeDef gpio_init = { 0 };

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