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hathachhathach
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Merge pull request #3294 from hathach/add-ohci-lpc55
try to enable ohci for lpc55 but not working, probably clock issue
2 parents 813eba2 + 3f1f714 commit fc3857e

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14 files changed

+163
-98
lines changed

14 files changed

+163
-98
lines changed

‎README.rst‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -160,23 +160,23 @@ Supported CPUs
160160
| +-----------------------------+--------+------+-----------+------------------------+-------------------+
161161
| | NUC505 | ✔ | | ✔ | nuc505 | |
162162
+--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+
163-
| NXP | iMXRT | RT 10xx, 11xx | ✔ | ✔ | ✔ | ci_hs | |
163+
| NXP | iMXRT | RT 10xx, 11xx | ✔ | ✔ | ✔ | ci_hs, ehci | |
164164
| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
165165
| | Kinetis | KL | ✔ | ⚠ | ✖ | ci_fs, khci | |
166166
| | +-------------------+--------+------+-----------+------------------------+-------------------+
167167
| | | K32L2 | ✔ | | ✖ | khci | ci_fs variant |
168168
| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
169169
| | LPC | 11u, 13, 15 | ✔ | ✖ | ✖ | lpc_ip3511 | |
170170
| | +-------------------+--------+------+-----------+------------------------+-------------------+
171-
| | | 17, 40 | ✔ | ⚠ | ✖ | lpc17_40 | |
171+
| | | 17, 40 | ✔ | ⚠ | ✖ | lpc17_40, ohci | |
172172
| | +-------------------+--------+------+-----------+------------------------+-------------------+
173-
| | | 18, 43 | ✔ | ✔ | ✔ | ci_hs | |
173+
| | | 18, 43 | ✔ | ✔ | ✔ | ci_hs, ehci | |
174174
| | +-------------------+--------+------+-----------+------------------------+-------------------+
175175
| | | 51u | ✔ | ✖ | ✖ | lpc_ip3511 | |
176176
| | +-------------------+--------+------+-----------+------------------------+-------------------+
177177
| | | 54, 55 | ✔ | | ✔ | lpc_ip3511 | |
178178
| +---------+-------------------+--------+------+-----------+------------------------+-------------------+
179-
| | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs | |
179+
| | MCX | N9 | ✔ | | ✔ | ci_fs, ci_hs, ehci | |
180180
| | +-------------------+--------+------+-----------+------------------------+-------------------+
181181
| | | A15 | ✔ | | | ci_fs | |
182182
+--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+

‎hw/bsp/lpc17/family.cmake‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,6 @@ function(family_configure_example TARGET RTOS)
6969
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
7070
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
7171
${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
72-
${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
7372
${TOP}/src/portable/ohci/ohci.c
7473
)
7574

‎hw/bsp/lpc17/family.mk‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
2020

2121
SRC_C += \
2222
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
23-
src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
2423
src/portable/ohci/ohci.c \
2524
$(MCU_DIR)/../gcc/cr_startup_lpc175x_6x.c \
2625
$(MCU_DIR)/src/chip_17xx_40xx.c \

‎hw/bsp/lpc40/family.cmake‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,6 @@ function(family_configure_example TARGET RTOS)
7070
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
7171
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
7272
${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c
73-
${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c
7473
${TOP}/src/portable/ohci/ohci.c
7574
)
7675

‎hw/bsp/lpc40/family.mk‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,6 @@ LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs
1818
# All source paths should be relative to the top level.
1919
SRC_C += \
2020
src/portable/nxp/lpc17_40/dcd_lpc17_40.c \
21-
src/portable/nxp/lpc17_40/hcd_lpc17_40.c \
2221
src/portable/ohci/ohci.c \
2322
$(MCU_DIR)/../gcc/cr_startup_lpc40xx.c \
2423
$(MCU_DIR)/src/chip_17xx_40xx.c \

‎hw/bsp/lpc55/boards/double_m33_express/board.cmake‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,6 @@ set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
77

88
set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/LPC55S69_cm33_core0_uf2.ld)
99

10-
# Device port default to PORT1 Highspeed
11-
if (NOT DEFINED PORT)
12-
set(PORT 1)
13-
endif()
14-
1510
function(update_board TARGET)
1611
target_compile_definitions(${TARGET} PUBLIC
1712
CPU_LPC55S69JBD100_cm33_core0

‎hw/bsp/lpc55/boards/lpcxpresso55s28/board.cmake‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,6 @@ set(JLINK_DEVICE LPC55S28)
55
set(PYOCD_TARGET LPC55S28)
66
set(NXPLINK_DEVICE LPC55S28:LPCXpresso55S28)
77

8-
# Device port default to PORT1 Highspeed
9-
if (NOT DEFINED PORT)
10-
set(PORT 1)
11-
endif()
12-
138
function(update_board TARGET)
149
target_compile_definitions(${TARGET} PUBLIC
1510
CPU_LPC55S28JBD100

‎hw/bsp/lpc55/boards/lpcxpresso55s69/board.cmake‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,6 @@ set(JLINK_DEVICE LPC55S69_M33_0)
55
set(PYOCD_TARGET LPC55S69)
66
set(NXPLINK_DEVICE LPC55S69:LPCXpresso55S69)
77

8-
# Device port default to PORT1 Highspeed
9-
if (NOT DEFINED PORT)
10-
set(PORT 1)
11-
endif()
12-
138
function(update_board TARGET)
149
target_compile_definitions(${TARGET} PUBLIC
1510
CPU_LPC55S69JBD100_cm33_core0

‎hw/bsp/lpc55/family.c‎

Lines changed: 55 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@
5555
#define IOCON_PIO_MODE_INACT 0x00u // No addition pin function
5656
#define IOCON_PIO_OPENDRAIN_DI 0x00u // Open drain is disabled
5757
#define IOCON_PIO_SLEW_STANDARD 0x00u // Standard mode, output slew rate control is enabled
58+
#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
5859

5960
#define IOCON_PIO_DIG_FUNC0_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC0) // Digital pin function 0 enabled
6061
#define IOCON_PIO_DIG_FUNC1_EN (IOCON_PIO_DIGITAL_EN | IOCON_PIO_FUNC1) // Digital pin function 1 enabled
@@ -197,13 +198,14 @@ void board_init(void) {
197198
USART_Init(UART_DEV, &uart_config, 12000000);
198199
#endif
199200

200-
// USB VBUS
201+
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 0)
201202
/* PORT0 PIN22 configured as USB0_VBUS */
202203
IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN);
203-
204-
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0
205204
// Port0 is Full Speed
206205

206+
NVIC_ClearPendingIRQ(USB0_IRQn);
207+
NVIC_ClearPendingIRQ(USB0_NEEDCLK_IRQn);
208+
207209
/* Turn on USB0 Phy */
208210
POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY);
209211

@@ -212,21 +214,55 @@ void board_init(void) {
212214
RESET_PeripheralReset(kUSB0HSL_RST_SHIFT_RSTn);
213215
RESET_PeripheralReset(kUSB0HMR_RST_SHIFT_RSTn);
214216

215-
// Enable USB Clock Adjustments to trim the FRO for the full speed controller
216-
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
217-
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
218-
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
219-
220-
/*According to reference manual, device mode setting has to be set by access usb host register */
221-
CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock
222-
USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
223-
CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
224-
225-
/* enable USB Device clock */
226-
CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
217+
if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 0) {
218+
// Enable USB Clock Adjustments to trim the FRO for the full speed controller
219+
ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK;
220+
CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false);
221+
CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
222+
223+
/*According to reference manual, device mode setting has to be set by access usb host register */
224+
CLOCK_EnableClock(kCLOCK_Usbhsl0); // enable usb0 host clock
225+
USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
226+
CLOCK_DisableClock(kCLOCK_Usbhsl0); // disable usb0 host clock
227+
/* enable USB Device clock */
228+
CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf));
229+
} else {
230+
const uint32_t port1_pin12_config = (/* Pin is configured as USB0_PORTPWRN */
231+
IOCON_PIO_FUNC4 |
232+
/* Selects pull-up function */
233+
IOCON_PIO_MODE_PULLUP |
234+
/* Standard mode, output slew rate control is enabled */
235+
IOCON_PIO_SLEW_STANDARD |
236+
/* Input function is not inverted */
237+
IOCON_PIO_INV_DI |
238+
/* Enables digital function */
239+
IOCON_PIO_DIGITAL_EN |
240+
/* Open drain is disabled */
241+
IOCON_PIO_OPENDRAIN_DI);
242+
/* PORT1 PIN12 (coords: 67) is configured as USB0_PORTPWRN */
243+
IOCON_PinMuxSet(IOCON, 1U, 12U, port1_pin12_config);
244+
245+
const uint32_t port0_pin28_config = (/* Pin is configured as USB0_OVERCURRENTN */
246+
IOCON_PIO_FUNC7 |
247+
/* Selects pull-up function */
248+
IOCON_PIO_MODE_PULLUP |
249+
/* Standard mode, output slew rate control is enabled */
250+
IOCON_PIO_SLEW_STANDARD |
251+
/* Input function is not inverted */
252+
IOCON_PIO_INV_DI |
253+
/* Enables digital function */
254+
IOCON_PIO_DIGITAL_EN |
255+
/* Open drain is disabled */
256+
IOCON_PIO_OPENDRAIN_DI);
257+
/* PORT0 PIN28 (coords: 66) is configured as USB0_OVERCURRENTN */
258+
IOCON_PinMuxSet(IOCON, 0U, 28U, port0_pin28_config);
259+
260+
CLOCK_EnableUsbfs0HostClock(kCLOCK_UsbfsSrcPll1, 48000000U);
261+
USBFSH->PORTMODE &= ~USBFSH_PORTMODE_DEV_ENABLE_MASK;
262+
}
227263
#endif
228264

229-
#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1
265+
#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1)
230266
// Port1 is High Speed
231267

232268
/* Turn on USB1 Phy */
@@ -266,9 +302,9 @@ void board_init(void) {
266302
// phytx |= USBPHY_TX_D_CAL(0x0C) | USBPHY_TX_TXCAL45DP(0x06) | USBPHY_TX_TXCAL45DM(0x06);
267303
// USBPHY->TX = phytx;
268304

269-
ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
270-
ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
271-
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
305+
ARM_MPU_SetMemAttr(0, 0x44); // Normal memory, non-cacheable (inner and outer)
306+
ARM_MPU_SetRegion(0, ARM_MPU_RBAR(0x40100000, ARM_MPU_SH_NON, 0, 1, 1), ARM_MPU_RLAR(0x40104000, 0));
307+
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
272308
#endif
273309
}
274310

‎hw/bsp/lpc55/family.cmake‎

Lines changed: 32 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -12,22 +12,40 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
1212

1313
set(FAMILY_MCUS LPC55 CACHE INTERNAL "")
1414

15-
if (NOT DEFINED PORT)
16-
set(PORT 0)
17-
endif()
15+
# ----------------------
16+
# Port & Speed Selection
17+
# ----------------------
1818

19-
# Host port will be the other port if available
20-
set(HOST_PORT $<NOT:${PORT}>)
19+
# default device port to USB1 highspeed, host to USB0 fullspeed
20+
if (NOT DEFINED RHPORT_DEVICE)
21+
set(RHPORT_DEVICE 1)
22+
endif ()
23+
if (NOT DEFINED RHPORT_HOST)
24+
set(RHPORT_HOST 0)
25+
endif ()
26+
27+
# port 0 is fullspeed, port 1 is highspeed
28+
set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
29+
30+
if (NOT DEFINED RHPORT_DEVICE_SPEED)
31+
list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
32+
endif ()
33+
if (NOT DEFINED RHPORT_HOST_SPEED)
34+
list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
35+
endif ()
36+
37+
cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
2138

2239
#------------------------------------
2340
# Startup & Linker script
2441
#------------------------------------
2542
if (NOT DEFINED LD_FILE_GNU)
26-
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
43+
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_CORE}_flash.ld)
2744
endif ()
2845
set(LD_FILE_Clang ${LD_FILE_GNU})
46+
2947
if (NOT DEFINED STARTUP_FILE_GNU)
30-
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
48+
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_CORE}.S)
3149
endif ()
3250
set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
3351

@@ -63,22 +81,20 @@ function(family_add_board BOARD_TARGET)
6381
)
6482
target_compile_definitions(${BOARD_TARGET} PUBLIC
6583
CFG_TUSB_MEM_ALIGN=TU_ATTR_ALIGNED\(64\)
66-
BOARD_TUD_RHPORT=${PORT}
67-
BOARD_TUH_RHPORT=${HOST_PORT}
84+
BOARD_TUD_RHPORT=${RHPORT_DEVICE}
85+
BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
86+
BOARD_TUH_RHPORT=${RHPORT_HOST}
87+
BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
6888
__STARTUP_CLEAR_BSS
6989
)
7090

7191
# Port 0 is Fullspeed, Port 1 is Highspeed. Port1 controller can only access USB_SRAM
72-
if (PORT EQUAL 1)
92+
if (RHPORT_DEVICE EQUAL 1)
7393
target_compile_definitions(${BOARD_TARGET} PUBLIC
74-
BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
75-
BOARD_TUH_MAX_SPEED=OPT_MODE_FULL_SPEED
7694
CFG_TUD_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
7795
)
78-
else ()
96+
elseif (RHPORT_HOST EQUAL 1)
7997
target_compile_definitions(${BOARD_TARGET} PUBLIC
80-
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
81-
BOARD_TUH_MAX_SPEED=OPT_MODE_HIGH_SPEED
8298
CFG_TUH_MEM_SECTION=__attribute__\(\(section\(\"m_usb_global\"\)\)\)
8399
)
84100
endif ()
@@ -98,6 +114,7 @@ function(family_configure_example TARGET RTOS)
98114
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
99115
${TOP}/lib/sct_neopixel/sct_neopixel.c
100116
${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c
117+
${TOP}/src/portable/ohci/ohci.c
101118
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
102119
)
103120
target_include_directories(${TARGET} PUBLIC

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